NXP Semiconductors PXN2020 - Page 1187

Nexus Development Interface (NDI)
PXN20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor 36-37
Table 36-25 shows the proper placement of data into the RWD. The “X” in the RWD column indicate byte
lanes with valid data.
Table 36-26 shows the mapping of RWD bytes to byte lanes of the AHB read and write data buses.
Nexus Reg: 0xA Access: User read/write
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Read/Write Data
W
Reset00000000000000000000000000000000
Figure 36-19. Read/Write Access Data Register (RWD)
Table 36-25. RWD Data Placement for Transfers
Transfer Size and byte offset RWA[2:0 RWCS[SZ]
RWD
31:24 23:16 15:8 7:0
Byte xxx 000 ——— X
Half Word xx0001——XX
Word x00 010 XXXX
Double Word 000 011
first RWD pass (low order data) XXXX
second RWD pass (high order data) XXXX
Table 36-26. RWD data placement for Transfers
Transfer Size and
byte offset
RWA[2:0]
RWD
31:24 23:16 15:8 7:0
Byte @000 000 — — — AHB[7:0]
Byte @001 001 — — — AHB[15:8]
Byte @010 010 — — — AHB[23:16]
Byte @011 011 — — — AHB[31:24]
Byte @100 100 — — — AHB[39:32]
Byte @101 101 — — — AHB[[47:40]
Byte @110 110 — — — AHB[55:48]
Byte @111 111 — — — AHB[63:56]
Half@000 000 — — AHB[15:8] AHB[7:0]
Half@010 010 — — AHB[31:24] AHB[23:16]
Half@100 100 — — AHB[[47:40] AHB[39:32]
Half@110 110 — — AHB[63:56] AHB[55:48]
Word@000 000 AHB[31:24] AHB[23:16] AHB[15:8] AHB[7:0]