FlexRay Communication Controller (FlexRAY)
PXN20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor 26-85
• Receive FIFO Watermark and Selection Register (RFWMSR)
• Receive FIFO Start Index Register (RFSIR)
• Receive FIFO Depth and Size Register (RFDSR)
• Receive FIFO Message ID Acceptance Filter Value Register (RFMIDAFVR)
• Receive FIFO Message ID Acceptance Filter Mask Register (RFMIAFMR)
• Receive FIFO Frame ID Rejection Filter Value Register (RFFIDRFVR)
• Receive FIFO Frame ID Rejection Filter Mask Register (RFFIDRFMR)
• Receive FIFO Range Filter Configuration Register (RFRFCFR)
26.6.3.7.2 Receive FIFO Control Data
The application can access the FIFOs at any time using the control bits in the following registers:
• Global Interrupt Flag and Enable Register (GIFER)
• Receive FIFO Fill Level and POP Count Register (RFFLPCR)
26.6.3.7.3 Receive FIFO Status Data
The current status of the receive fifo is provided in the following register:
• Global Interrupt Flag and Enable Register (GIFER)
• Receive FIFO A Read Index Register (RFARIR)
• Receive FIFO B Read Index Register (RFBRIR)
• Receive FIFO Fill Level and POP Count Register (RFFLPCR)
26.6.4 FlexRay Memory Layout
The controller supports a wide range of possible layouts for the FlexRay memory. Two basic layout modes
can be selected by the FIFO address mode bit MCR[FAM].
26.6.4.1 FlexRay Memory Layout (MCR[FAM] = 0)
Figure 26-107 shows an example layout for the FIFO address mode MCR[FAM] = 0. In this mode, the
following set of rules applies to the layout of the FlexRay memory:
• The FlexRay memory is one contiguous region.
• The FlexRay memory size is maximum 64 Kbytes.
• The FlexRay memory starts at a 16 byte boundary
The FlexRay memory contains three areas: the message buffer header area, the message buffer data area,
and the sync frame table area.
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