Enhanced Modular Input/Output Subsystem (eMIOS200)
PXN20 Microcontroller Reference Manual, Rev. 1
28-8 Freescale Semiconductor
28.3.2 Register Descriptions
This section lists the eMIOS200 registers in address order and describes the registers and their bit fields.
Unified Channel 3–31 Registers
3
0x0080–0x041F Same as other Channel Registers (e.g. EMIOS_CADR[2],
EMIOS_CBDR[2], etc.)
—— —
0x0420–0x3FFF Reserved
1
Note that R/W registers may contain some read-only or write-only bits.
2
The alternate address register provides and alternate read-only address to access A2 channel registers in pulse edge counting
(PEC) and windowed programmable time accumulation (WPTA) modes. IF EMIOS_CADR[n] register is used with
EMIOS_ALTA[n], both A1 and A2 registers can be accessed in these modes.
3
For a complete list of Unified Channel registers with their addresses, please see eMIOS_A in Appendix A, Memory Map.
Table 28-4. Unified Channel Base Offsets
Unified Channel
Offset from
EMIOS_BASE
(0xFFFE_4000)
Unified Channel
Offset from
EMIOS_BASE
(0xFFFE_4000)
Unified Channel 0 0x0020 Unified Channel 16 0x0220
Unified Channel 1 0x0040 Unified Channel 17 0x0240
Unified Channel 2 0x0060 Unified Channel 18 0x0260
Unified Channel 3 0x0080 Unified Channel 19 0x0280
Unified Channel 4 0x00A0 Unified Channel 20 0x02A0
Unified Channel 5 0x00C0 Unified Channel 21 0x02C0
Unified Channel 6 0x00E0 Unified Channel 22 0x02E0
Unified Channel 7 0x0100 Unified Channel 23 0x0300
Unified Channel 8 0x0120 Unified Channel 24 0x0320
Unified Channel 9 0x0140 Unified Channel 25 0x0340
Unified Channel 10 0x0160 Unified Channel 26 0x0360
Unified Channel 11 0x0180 Unified Channel 27 0x0380
Unified Channel 12 0x01A0 Unified Channel 28 0x03A0
Unified Channel 13 0x01C0 Unified Channel 29 0x03C0
Unified Channel 14 0x01E0 Unified Channel 30 0x03E0
Unified Channel 15 0x0200 Unified Channel 31 0x0400
Table 28-3. eMIOS200 Memory Map (continued)
Offset from
EMIOS_BASE
(0xFFFE_4000)
Register Access
1
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