Enhanced Serial Communication Interface (eSCI)
PXN20 Microcontroller Reference Manual, Rev. 1
31-10 Freescale Semiconductor
31.3.2.4 eSCI Data Register (eSCI_DR)
This register is used to provide transmit data and retrieve received data in SCI mode. In LIN mode any
write access to this register is ignored and any read access returns all 0. In case of data transmission this
register is used to provide a part of the transmit data. In case of data reception this register provides a part
of the received data and related error information.
If the application writes to the lower byte of this register (eSCI_SDR[7:0]), the internal commit flag iCMT,
which is not visible to the application, is set to indicate that the register has been updated and ready to
transmit new data.
If the application reads from the lower byte of this register (eSCI_SDR[7:0]), a signal is send to the internal
receiver unit to indicate that the register was r
PMSK Parity Bit Masking. This bit defines whether the received parity bit is presented in the related bit position in the
SCI Data Register (eSCI_SDR).
0 The received parity bit is presented in the bit position related to the parity bit.
1 The value 0 is presented in the bit position related to the parity bit.
ORIE Overrun Interrupt Enable. This bit controls the eSCI_IFSR1[OR] interrupt request generation.
0 OR interrupt request generation disabled.
1 OR interrupt request generation enabled.
NFIE Noise Interrupt Enable. This bit controls the eSCI_IFSR1[NF] interrupt request generation.
0 NF interrupt request generation disabled.
1 NF interrupt request generation enabled.
FEIE Frame Error Interrupt Enable. This bit controls the eSCI_IFSR1[FE] interrupt request generation.
0 FE interrupt request generation disabled.
1 FE interrupt request generation enabled.
PFIE Parity Error Interrupt Enable. This bit controls the eSCI_IFSR1[PF] interrupt request generation.
0 PF interrupt request generation disabled.
1 PF interrupt request generation enabled.
Offset: ESCI_BASE + 0x0006 Access: User read/write
0123456789101112131415
RRN
TN
ERR 0 RD[11:8] RD[7] RD[6:0]
W TD[7] TD[6:0]
Reset0000000000000000
Figure 31-5. eSCI Data Register (eSCI_DR)
Table 31-5. eSCI_CR2 Field Descriptions (continued)
Field Description
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