Enhanced Serial Communication Interface (eSCI)
PXN20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor 31-9
Table 31-5. eSCI_CR2 Field Descriptions
Field Description
MDIS Module Disabled Mode. This bit controls the module mode of operation, which is described in Section 31.1.3,
Modes of Operation.
0 Module is not in disabled mode.
1 Module is in disabled mode.
FBR Fast Bit Error Detection. This bit controls the Bit Error Detection mode.
0 Standard bit error detection performed as described in
Note: 1Fast bit error detection performed as described in This bit is used in LIN mode only.
BSTP DMA Stop on Bit Error or Physical Bus Error. This bit controls the transmit DMA requests generation in case of
bit errors or physical bus errors. Bit errors are indicated by the BERR flag in the Interrupt Flag and Status Register
1 (eSCI_IFSR1) and physical bus errors are indicated by the PBERR flag in the Interrupt Flag and Status
Register 2 (eSCI_IFSR2).
0 Transmit DMA requests generated regardless of bit errors or physical bus errors.
1 Transmit DMA requests are not generated if eSCI_IFSR1[BERR] or eSCI_IFSR2[PBERR] flags are set.
Note: This bit is used in LIN mode only.
BERRIE Bit Error Interrupt Enable. This bit controls the BERR interrupt request generation.
0 BERR interrupt request generation disabled.
1 BERR interrupt request generation enabled.
RXDMA Receive DMA Control. This bit enables the receive DMA feature.
0 Receive DMA disabled.
1 Receive DMA enabled.
TXDMA Transmit DMA Control. This bit enables the transmit DMA feature.
0 Transmit DMA disabled.
1 Transmit DMA enabled.
BRCL Break Character Length. This bit is used to define the length of the break character to be transmitted.
The settings are specified in Section 31.4.2.2, Break Character Formats.
TXDIR TXD pin output enable. This bit determines whether the TXD pin is used as an output.
0 TXD pin is not used as output.
1 TXD pin is used as output.
Note: This bit is used in Single Wire Mode only.
BESM Fast Bit Error Detection Sample Mode. This bit defines the sample point for the fast bit error detection mode.
0 Sample point is RS9.
1 Sample point is RS13.
Note: This bit is used in LIN mode only.
BESTP Transmit Stop on Bit Error. If this control bit is set, the eSCI stops driving the LIN bus immediately when a Bit
Error has been detected, i.e. eSCI_IFSR1[BERR] = 1. Additionally, the eSCI will not start a new byte
transmission as long the BERR interrupt flag is set.
0 Transmission is not stopped on bit error.
1 Transmission is stopped on bit error.
Note: This bit is used in LIN mode only.
RXPOL RXD Pin polarity. This bit controls the polarity of the RXD pin. See Section 31.4.2.1.1, Inverted Data Frame
Formats.
0 Normal Polarity.
1 Inverted Polarity.
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