Deserial – Serial Peripheral Interface (DSPI)
PXN20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor 30-41
DSPI_CTARn[BR]) to produce SCK with the possibility of halving the scaler division. The DBR, PBR,
and BR fields in the DSPI_CTARn registers select the frequency of SCK using the following formula:
Eqn. 30-5
Table 30-26 shows an example of a computed baud rate.
30.4.7.2 PCS to SCK Delay (t
CSC
)
The PCS to SCK delay is the length of time from assertion of the PCS signal to the first SCK edge. See
Figure 30-29 for an illustration of the PCS to SCK delay. The PCSSCK and CSSCK fields in the
DSPI_CTARn registers select the PCS to SCK delay, and the relationship is expressed by the following
formula:
Eqn. 30-6
Table 30-27 shows an example of the computed PCS to SCK delay.
30.4.7.3 After SCK Delay (t
ASC
)
The after SCK delay is the length of time between the last edge of SCK and the negation of PCS. See
Figure 30-29 and Figure 30-30 for illustrations of the after SCK delay. The PASC and ASC fields in the
DSPI_CTARn registers select the after SCK delay. The relationship between these variables is given in the
following formula:
Table 30-28 shows an example of the computed after SCK delay.
Table 30-26. Baud Rate Computation Example
f
SYS PBR
Prescaler
Value
BR
Scaler
Value
DBR
Value
Baud Rate
66 MHz 0b00 2 0b0000 2 0 16.67 Mbit/s
20 MHz 0b00 2 0b0000 2 1 10 Mbit/s
Table 30-27. PCS to SCK Delay Computation Example
PCSSCK
Prescaler
Value
CSSCK
Scaler
Value
f
SYS PCS to SCK Delay
0b01 3 0b0100 32 100 MHz 0.96 µs
SCK baud rate
f
SYS
PBRPrescalerValue
----------------------------------------------------------
1DBR+
BRScalerValue
--------------------------------------------
=
t
CSC
=
f
SYS
CSSCK
PCSSCK
1
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