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NXP Semiconductors PXN2020 - 25.3.1 Top Level Module Memory Map; 25.3.2 Detailed Memory Map (Control;Status Registers)

NXP Semiconductors PXN2020
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Fast Ethernet Controller (FEC)
PXN20 Microcontroller Reference Manual, Rev. 1
25-6 Freescale Semiconductor
25.3.1 Top Level Module Memory Map
The FEC implementation requires a 1 KB memory map space. This is divided into two sections of 512
bytes each. The first is used for control/status registers. The second contains event/statistic counters held
in the MIB block. Table 25-1 defines the top level memory map. All accesses to and from the FEC memory
map must be via 32-bit accesses. There is no support for accesses other than 32-bit.
25.3.2 Detailed Memory Map (Control/Status Registers)
Table 25-2 shows the FEC register memory map with each register address, name, and a brief description.
The base address of the FEC registers is 0xFFF4_C000.
NOTE
Some memory locations are not documented. The actual FEC memory map
is from 0xFFF4_C000 to 0xFFF4_C5FF. Also, some bits in otherwise
documented registers are not documented. These memory locations and bits
are not needed for the FEC software driver. They are used mainly by the
FEC subblocks for the FEC operation and happen to be visible through the
slave interface.
Errant writes to these locations can corrupt FEC operation. Because the FEC
is a system bus master, errant writes also can result in the corruption of any
memory mapped location in the system. However, even errant writes to
documented FEC memory locations can cause the same corruption.
Table 25-1. FEC Module Memory Map
Address Function
FFF4_C000 (Base Address) –
FFF4_C1FF
Control/Status Registers
FFF4_C200 – FFF4_C3FF MIB Block Counters
Table 25-2. FEC Register Memory Map
Offset from
FEC_BASE
(0xFFF4_C000)
Register Access
1
Reset Value Section/Page
0x0000–0x0003 Reserved
0x0004 EIR—Interrupt Event Register R/W 0x0000_0000 25.3.4.2/25-10
0x0008 EIMR—Interrupt Mask Register R/W 0x0000_0000 25.3.4.3/25-12
0x000C–0x000F Reserved
0x0010 RDAR—Receive Descriptor Active Register R/W 0x0000_0000 25.3.4.4/25-12
0x0014 TDAR—Transmit Descriptor Active Register R/W 0x0000_0000 25.3.4.5/25-13
0x0018–0x0023 Reserved
0x0024 ECR—Ethernet Control Register R/W 0xF000_0000 25.3.4.6/25-14

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