NXP Semiconductors PXN2020 - Page 573

Fast Ethernet Controller (FEC)
PXN20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor 25-7
0x0028–0x003F Reserved
0x0040 MMFR—MII Management Frame Register R/W U 25.3.4.7/25-15
0x0044 MSCR—MII Speed Control Register R/W 0x0000_0000 25.3.4.8/25-16
0x0048–0x0063 Reserved
0x0064 MIBC—MIB Control/Status Register R/W 0xC000_0000 25.3.4.9/25-18
0x0068–0x0083 Reserved
0x0084 RCR—Receive Control Register R/W 0x05EE_0001 25.3.4.10/25-18
0x0088–0x00C3 Reserved
0x00C4 TCR—Transmit Control Register R/W 0x0000_0000 25.3.4.11/25-20
0x00C8–0x00E3 Reserved
0x00E4 PALR—MAC Address Low Register R/W U 25.3.4.12/25-21
0x00E8 PAUR—MAC Address Upper Register + Type Field R/W 0xUUUU_8808 25.3.4.13/25-21
0x00EC OPD—Opcode + Pause Duration Fields R/W 0x0001_UUUU 25.3.4.14/25-22
0x00F0–0x0117 Reserved
0x0118 IAUR—Upper 32 bits of Individual Hash Table R/W U 25.3.4.15/25-23
0x011C IALR—Lower 32 Bits of Individual Hash Table R/W U 25.3.4.16/25-23
0x0120 GAUR—Upper 32 bits of Group Hash Table R/W U 25.3.4.17/25-24
0x0124 GALR—Lower 32 bits of Group Hash Table R/W U 25.3.4.18/25-25
0x0128–0x0143 Reserved
0x0144 TFWR—Transmit FIFO Watermark R/W 0x0000_0000 25.3.4.19/25-25
0x0148–0x014B Reserved
0x014C FRBR—FIFO Receive Bound Register R/W 0x0000_0600 25.3.4.20/25-26
0x0150 FRSR—FIFO Receive FIFO Start Registers R/W 0x0000_0500 25.3.4.21/25-27
0x0154–0x017F Reserved
0x0180 ERDSR—Pointer to Receive Descriptor Ring R/W U 25.3.4.22/25-27
0x0184 ETDSR—Transmit Buffer Descriptor Ring Start Register R/W U 25.3.4.23/25-28
0x0188 EMRBR—Receive Buffer Size Register R/W U 25.3.4.24/25-29
0x018C–0x3FFF Reserved
1
All accesses to and from the FEC memory map must be via 32-bit accesses. There is no support for accesses other than 32-bit.
Table 25-2. FEC Register Memory Map (continued)
Offset from
FEC_BASE
(0xFFF4_C000)
Register Access
1
Reset Value Section/Page