NXP Semiconductors PXN2020 - 24.3.2.4 eDMA Enable Error Interrupt Register (EDMA

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Enhanced Direct Memory Access Controller (eDMA)

PXN20 Microcontroller Reference Manual, Rev. 1

Freescale Semiconductor 24-13

Both the eDMA request input signal and this enable request flag must be asserted before a channel’s

hardware service request is accepted. The state of the eDMA enable request flag does not effect a channel

service request made through software or a linked channel request.

As a given channel completes processing its major iteration count, there is a flag in the transfer control

descriptor that may affect the ending state of the EDMA_ERQR bit for that channel. If the TCD.D_REQ

bit is set, then the corresponding EDMA_ERQR bit is cleared after the major loop is complete, disabling

the eDMA hardware request. Otherwise if the D_REQ bit is cleared, the state of the EDMA_ERQR bit is

unaffected.

24.3.2.4 eDMA Enable Error Interrupt Register (EDMA_EEIRL)

The EDMA_EEIRL provides a bit map for the 32 channels to enable the error interrupt signal for each

channel. EDMA_EEIRL maps to channels 31–0.

The state of any given channel’s error interrupt enable is directly affected by writes to these registers; it is

also affected by writes to the EDMA_SEEIR and EDMA_CEEIR. The EDMA_SEEIR and

EDMA_CEEIR are provided so that the error interrupt enable for a single channel can be modified without

the performing a read-modify-write sequence to the EDMA_EEIRL.

Both the eDMA error indicator and this error interrupt enable flag must be asserted before an error

interrupt request for a given channel is asserted.

Offset: EDMA_BASE + 0x000C Access: User read/write

0123456789101112131415

ERQ

Reset0000000000000000

16 17 19 19 20 21 22 23 24 25 26 27 28 29 30 31

ERQ

Reset0000000000000000

Figure 24-4. eDMA Enable Request Register (EDMA_ERQRL)

Table 24-5. EDMA_ERQRL Field Descriptions

Field Description

ERQn Enable eDMA Hardware Service Request n.

0 The eDMA request signal for channel n is disabled.

1 The eDMA request signal for channel n is enabled.

NXP Semiconductors PXN2020 - 24.3.2.4 eDMA Enable Error Interrupt Register (EDMA_EEIRL)