NXP Semiconductors PXN2020 - 1.3 PXN20 Block Diagram

Introduction
PXN20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor 1-3
Similarly, the e200z0 core is also referred to as the Z0.
1.3 PXN20 Block Diagram
Figure 1-1 shows a top-level block diagram of the PXN20.
Figure 1-1. PXN20 Block Diagram
Crossbar Switch (XBAR)
PXN20 Block Diagram
VLE
MMU (32 TLB)
32 KB Cache
e200z650 Core
FPU/SPE
Debug
JTAG
Nexus3 (Z6)
Nexus2+ (Z0)
4/8 Way
4-40 MHz
XTAL
Masters
32 kHz
XTAL
16 MHz
IRC
e200z0 Core
VLE
Semaphores
16-ch DMA
Mux
128 kHz
IRC
FMPLL
2 MB
ECSM
512 KB
Standby RAM
ECSM
PBRIDGE B
6 x UART/LIN
36 x ADC
24 x eMIOS
2 x I
2
C
2 x SPI
6 x CAN
PBRIDGE A
2 x SPI
2 x I
2
C
SRAM
(ECC)
Flash
(ECC)
80 KB
ECSM
SRAM
(ECC)
Ethernet MLB-DIM FlexRay™
VREG
Controller
SWT
STM
RTC/API
INTC
PIT
BAM
SIU
ADC – Analog-to-digital converter
BAM – Boot assist module
CAN – Controller area network controller
ECC – Error correction code
ECSM – Error correction status module
eMIOS – Timed input/output
eDMA – Enhanced direct memory access controller
FEC – Fast ethernet controller
FlexRay™ – FlexRay bus controller
FMPLL – Frequency-modulated phase-locked loop
I
2
C – Inter-integrated circuit controller
INTC – Interrupt controller
JTAG – Joint Test Action Group interface
MLB-DIM – Media Local Bus device interface module
NDI – Nexus debug interface
PBRIDGE– Peripheral I/O bridge
PIT – Periodic interrupt timer
RTC – Real time clock
SIU – System integration unit
SPI – Serial peripheral interface controller
STM – System timer module
SWT – Software watchdog timer
UART/LIN – Universal asynchronous receiver/transmitter/
local interconnect network
VREG – Voltage regator