NXP Semiconductors PXN2020 - 21.3.2.5 STM Channel Compare Register (STM_CMPn); 21.4 Functional Description

System Timer Module (STM)
PXN20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor 21-5
21.3.2.5 STM Channel Compare Register (STM_CMPn)
The STM channel compare register (STM_CMPn) holds the compare value for channel n.
21.4 Functional Description
The System Timer Module (STM) is a 32-bit timer designed to support commonly required system and
application software timing functions. The STM includes a 32-bit up counter and four 32-bit compare
channels with a separate interrupt source for each channel.
The STM has one 32-bit up counter (STM_CNT) that is used as the time base for all channels. When
enabled, the counter increments at the system clock frequency divided by a prescale value. The
STM_CR[CPS] field sets the divider to any value in the range from 1 to 256. The counter is enabled with
the STM_CR[TEN] bit. When enabled in normal mode the counter continuously increments. When
enabled in debug mode the counter operation is controlled by the STM_CR[FRZ] bit. When the
STM_CR[FRZ] bit is set, the counter is stopped in debug mode, otherwise it continues to run in debug
mode. The counter rolls over at 0xFFFF_FFFF to 0x0000_0000 with no restrictions at this boundary.
The STM has four identical compare channels. Each channel includes a channel control register
(STM_CCRn), a channel interrupt register (STM_CIRn) and a channel compare register (STM_CMPn).
The channel is enabled by setting the STM_CCRn[CEN] bit. When enabled, the channel sets the
STM_CIRn[CIF] bit and generate an interrupt request when the channel compare register matches the
timer counter. The interrupt request is cleared by writing a 1 to the STM_CIRn[CIF] bit. A write of 0 to
the STM_CIRn[CIF] bit has no effect.
Table 21-5. STM_CIRn Field Descriptions
Field Description
CIF Channel Interrupt Flag. The flag and interrupt are cleared by writing a 1 to this bit. Writing a 0 has no effect.
0 No interrupt request.
1 Interrupt request due to a match on the channel.
Offset: STM_CMP0: STM_BASE + 0x0018
STM_CMP1: STM_BASE + 0x0028
STM_CMP2: STM_BASE + 0x0038
STM_CMP3: STM_BASE + 0x0048
Access: User read/write
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
CMP
W
Reset00000000000000000000000000000000
Figure 21-5. STM Channel Compare Register (STM_CMPn)
Table 21-6. STM_CMPn Register Field Descriptions
Field Description
CMP Compare value for channel n. If the STM_CCRn[CEN] bit is set and the STM_CMPn register matches the
STM_CNTn register, a channel interrupt request is generated and the STM_CIRn[CIF] bit is set.