NXP Semiconductors PXN2020 - 8.3.2.20 External Clock Control Register (SIU_ECCR)

System Integration Unit (SIU)
PXN20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor 8-37
8.3.2.20 External Clock Control Register (SIU_ECCR)
The SIU_ECCR controls the timing relationship between the system clock and the external clocks,
CLKOUT. All bits and fields in the SIU_ECCR are read/write and reset by the asynchronous reset signal.
Offset: SIU_BASE + 0x0984 Access: User read-only
0123456789101112131415
R0000000000000000
W
Reset0000000000000000
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
000
ECEN
0
ECDF
W
Reset0001000000000001
1
Writes to this bit have no effect, but reads return the written value.
Figure 8-23. External Clock Control Register (SIU_ECCR)
Table 8-25. SIU_ECCR Field Descriptions
Field Description
ECEN External Clock Enable. The ECEN bit enables CLKOUT. The CLKOUT waveform is determined by ECDF divides
relative to the internal system clock.
Note: To correctly reflect the CLKOUT waveform to the external pin, the SIU_PCR for the CLKOUT pin needs to
be configured.
0 Disable CLKOUT waveform.
1 Enable CLKOUT waveform.
ECDF External Clock Division Factor. Specifies frequency ratio between system clock and external clock, CLKOUT. The
CLKOUT frequency is divided from the system clock frequency according to the descriptions below.
00 Divide by 1.
01 Divide by 2 (default value).
10 Divide by 4.
11 Divide by 8.
Note: If ECDF is equal to 0b00 and SIU_SYSCLK[SYSCLKDIV] is not equal to 0b000, then the CLKOUT pin will
not have a nominal 50% duty cycle.