NXP Semiconductors PXN2020 - 18.3.2 Register Descriptions; 18.3.2.1 MPU Control;Error Status Register (MPU_CESR)

Memory Protection Unit (MPU)
PXN20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor 18-5
18.3.2 Register Descriptions
This section lists the MPU registers in address order and describes the registers and their bit fields.
18.3.2.1 MPU Control/Error Status Register (MPU_CESR)
The MPU_CESR provides one byte of error status and three bytes of configuration information. A global
MPU enable/disable bit is also included in this register.
0x080C MPU_RGDAAC3—MPU RGD alternate access control 3 W —
1
18.3.2.5/18-13
0x0810 MPU_RGDAAC4—MPU RGD alternate access control 4 W —
1
18.3.2.5/18-13
0x0814 MPU_RGDAAC5—MPU RGD alternate access control 5 W —
1
18.3.2.5/18-13
0x0818 MPU_RGDAAC6—MPU RGD alternate access control 6 W —
1
18.3.2.5/18-13
0x081C MPU_RGDAAC7—MPU RGD alternate access control 7 W —
1
18.3.2.5/18-13
0x0820 MPU_RGDAAC8—MPU RGD alternate access control 8 W —
1
18.3.2.5/18-13
0x0824 MPU_RGDAAC9—MPU RGD alternate access control 9 W —
1
18.3.2.5/18-13
0x0828 MPU_RGDAAC10—MPU RGD alternate access control 10 W —
1
18.3.2.5/18-13
0x082C MPU_RGDAAC11—MPU RGD alternate access control 11 W —
1
18.3.2.5/18-13
0x0830 MPU_RGDAAC12—MPU RGD alternate access control 12 W —
1
18.3.2.5/18-13
0x0834 MPU_RGDAAC13—MPU RGD alternate access control 13 W —
1
18.3.2.5/18-13
0x0838 MPU_RGDAAC14—MPU RGD alternate access control 14 W —
1
18.3.2.5/18-13
0x083C MPU_RGDAAC15—MPU RGD alternate access control 15 W —
1
18.3.2.5/18-13
0x0840–0x08FF Reserved
1
See register definition.
Offset: MPU_BASE + 0x0000 Access: User read/write
0123456789101112131415
R
MPERR
1
1000 HRL
W
Reset0000000010000000
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R NSP NRGD 0 0 000 0 0
VLD
W
Reset0100001000000000
Figure 18-3. MPU Control/Error Status Register (MPU_CESR)
Table 18-2. MPU Memory Map (continued)
Offset from
MPU_BASE
(0xFFF1_4000)
Register Access Reset Value Section/Page