NXP Semiconductors PXN2020 - 31.3.2.3 eSCI Control Register 2 (eSCI_CR2)

Enhanced Serial Communication Interface (eSCI)
PXN20 Microcontroller Reference Manual, Rev. 1
31-8 Freescale Semiconductor
31.3.2.3 eSCI Control Register 2 (eSCI_CR2)
This register provides bits to configure the functionality of the module, and interrupt enable bits for the
interrupt flags provided in eSCI Interrupt Flag and Status Register 1 (eSCI_IFSR1) and control bits for the
transmitter and receiver.
RWU Receiver Wake-Up Mode. This bit controls and indicates the receiver wake-up mode, which is described in
Section 31.4.5.5, Multiprocessor Communication.
0 Normal receiver operation.
1 Receiver is in wake-up mode.
Note: This bit should be set in SCI mode only.
SBK Send Break Character. This bit controls the transmission of break characters, which is described in
Section 31.4.5.2.7, Break Character Transmission.
0 No break characters are transmitted.
1 Break characters are transmitted.
Note: This bit should be set in SCI mode only.
Table 31-4. Receive Source Mode Selection
LOOPS RSCR Receiver Input Mode
0 0 Dual Wire Mode
01 Reserved
1 0 Loop Mode
1 1 Single Wire Mode
Offset: ESCI_BASE + 0x0004 Access: User read/write
0123456789101112131415
R
MDIS FBR BSTP
BERR
IE
RX
DMA
TX
DMA
BRCL
TX
DIR
BE
SM
BE
STP
RX
POL
P
MSK
ORIE NFIE FEIE PFIE
W
Reset1010000000000000
Figure 31-4. eSCI Control Register 2 (eSCI_CR2)
Table 31-3. eSCI_CR1 Field Descriptions (continued)
Field Description