Enhanced Serial Communication Interface (eSCI)
PXN20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor 31-7
Table 31-3. eSCI_CR1 Field Descriptions
Field Description
LOOPS Loop Mode Select. Together with the RSRC control bit, this control bit defines the receiver source mode. The
mode coding is defined in Ta ble 31 -4 and the modes are described in Section 31.4.5.3.2, Receiver Input Mode
Selection.
RSRC Receiver Source Control. Together with the LOOPS control bit, this control bit defines the receiver source mode.
The mode coding is defined in Ta ble 3 1- 4 and the modes are described in Section 31.4.5.3.2, Receiver Input
Mode Selection.
M Frame Format Mode. Together with the M2 bit of the eSCI Control Register 3 (eSCI_CR3), this control bit controls
the frame format used. The supported frame formats and the related settings are described in Section 31.4.2,
Frame Formats.
WAKE Receiver Wake-up Condition. This control bit defines the wake-up condition for the receiver. The receiver
wake-up is described in Section 31.4.5.5, Multiprocessor Communication.
0 Idle line wake-up.
1 Address mark wake-up
ILT Idle Line Type. This control bit defines the type of idle line detection for the receiver wake-up. The two types are
described in Section 31.4.5.5.1, Idle-Line Wakeup.
0 Idle line detection starts after reception of a low bit.
1 Idle line detection starts after reception of the last stop bit.
PE Parity Enable. This control bit enables the parity bit generation and checking. The location of the parity bits is
shown in Section 31.4.2, Frame Formats.
0 Parity bit generation and checking disabled.
1 Parity bit generation and checking enabled.
PT Parity Type. This control bit defines whether even or odd parity has to be used.
0 Even parity (even number of ones in character clears the parity bit).
1 Odd parity (odd number of ones in character clears the parity bit).
TIE Transmitter Interrupt Enable. This bit controls the eSCI_IFSR1[TRDE] interrupt request generation.
0 TDRE interrupt request generation disabled.
1 TDRE interrupt request generation enabled.
TCIE Transmission Complete Interrupt Enable. This bit controls the eSCI_IFSR1[TC] interrupt request generation.
0 TC interrupt request generation disabled.
1 TC interrupt request generation enabled.
RIE Receiver Full Interrupt Enable. This bit controls the eSCI_IFSR1[RDRF] interrupt request generation.
0 RDRF interrupt request generation disabled.
1 RDRF interrupt request generation enabled.
ILIE Idle Line Interrupt Enable. This bit controls eSCI_IFSR1[IDLE] interrupt request generation.
0 IDLE interrupt request generation disabled.
1 IDLE interrupt request generation enabled.
TE Transmitter Enable. This control bit enables and disables the transmitter. The control features of the transmitter
are described in Section 31.4.5.2.1, Transmitter States and Transitions.
0 Transmitter disabled.
1 Transmitter enabled.
RE Receiver Enable.This control bit enables and disables the receiver. The control features of the receiver are
described in Section 31.4.5.3.1, Receiver States and Transitions.
0 Receiver disabled.
1 Receiver enabled.
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