NXP Semiconductors PXN2020 - 30.4.7.4 Delay after Transfer (tDT)

Deserial – Serial Peripheral Interface (DSPI)
PXN20 Microcontroller Reference Manual, Rev. 1
30-42 Freescale Semiconductor
30.4.7.4 Delay after Transfer (t
DT
)
The delay after transfer is the length of time between negation of the PCS signal for a frame and the
assertion of the PCS signal for the next frame. See Figure 30-29 for an illustration of the delay after
transfer. The PDT and DT fields in the DSPI_CTARn registers select the delay after transfer. The
following formula expresses the PDT/DT/delay after transfer relationship:
Eqn. 30-7
Table 30-29 shows an example of the computed delay after transfer.
When in non-continuous clock mode the T
DT
delay is configurable as outlined in the DSPI_CTARn
registers. When in continuous clock mode and TSB is not enabled the delay is fixed at 1 SCK period. When
in TSB and continuous mode, the delay is programmed as outlined in the DSPI_CTARn registers. In event
that the delay does not coincide with an SCK period in duration, the delay is extended to the next SCK
active edge. Table 30-30 shows an example of how to compute the delay after Transfer with the clock
period of SCK defined as T
SCK
. The values calculated assume 1TSCK period = 4 ipg_clk.
Table 30-28. After SCK Delay Computation Example
PASC
Prescaler
Value
ASC
Scaler
Value
Fsys After SCK Delay
0b01 3 0b0100 32 100 MHz 0.96 us
Table 30-29. Delay after Transfer Computation Example
PDT
Prescaler
Value
DT
Scaler
Value
f
SYS Delay after Transfer
0b01 3 0b1110 32768 100 MHz 0.98 ms
t
DT
=
f
SYS
DT

PDT
1
