Controller Area Network (FlexCAN)
PXN20 Microcontroller Reference Manual, Rev. 1
29-22 Freescale Semiconductor
Table 29-11. CANx_ESR Field Descriptions
Field Description
TWRN_INT If the WRN_EN bit in CANx_MCR is set, the TWRN_INT bit is set when the TXWRN flag transitions from 0 to
1, meaning that the Tx error counter reached 96. If the corresponding mask bit in the CANx_CTRL register
(TWRN_MSK) is set, an interrupt is generated to the CPU. This bit is cleared by writing to 1. Writing 0 has no
effect.
0 No such occurrence.
1 TXECTR 96.
RWRN_INT If the WRN_EN bit in CANx_MCR is set, the RWRN_INT bit is set when the RXWRN flag transitions from 0 to
1, meaning that the Rx error counter reached 96. If the corresponding mask bit in the CANx_CTRL register
(RWRNMSK) is set, an interrupt is generated to the CPU. This bit is cleared by writing to 1. Writing 0 has no
effect.
0 No such occurrence.
1 RXECTR 96.
BIT1_ERR Bit 1 Error. Indicates when an inconsistency occurs between the transmitted and the received message in a bit.
A read clears BIT1_ERR.
0 No such occurrence.
1 At least one bit sent as recessive is received as dominant.This bit is not set by a transmitter in case of
arbitration field or ACK slot, or in case of a node sending a passive error flag that detects dominant bits.
Note: This bit is not set by a transmitter in case of arbitration field or ACK slot, or in case of a node sending a
passive error flag that detects dominant bits.
BIT0_ERR Bit 0 Error. Indicates when an inconsistency occurs between the transmitted and the received message in a bit.
A read clears BIT0_ERR.
0 No such occurrence.
1 At least one bit sent as dominant is received as recessive.
ACK_ERR Acknowledge Error. Indicates that an acknowledge error has been detected by the transmitter node; that is, a
dominant bit has not been detected during the ACK SLOT. A read clears ACK_ERR.
0 No such occurrence.
1 An ACK error occurred since last read of this register.
CRC_ERR Cyclic Redundancy Code Error. Indicates that a CRC error has been detected by the receiver node; that is, the
calculated CRC is different from the received. A read clears CRC_ERR.
0 No such occurrence.
1 A CRC error occurred since last read of this register.
FRM_ERR Form Error. Indicates that a form error has been detected by the receiver node; that is, a fixed-form bit field
contains at least one illegal bit. A read clears FRM_ERR.
0 No such occurrence.
1 A form error occurred since last read of this register.
STF_ERR Stuffing Error. Indicates that a stuffing error has been detected. A read clears STF_ERR.
0 No such occurrence.
1 A stuffing error occurred since last read of this register.
TX_WRN Tx Error Counter. This status bit indicates that repetitive errors are occurring during message transmission. A
read clears TX_WRN.
0 No such occurrence.
1 TXECTR 96.
RX_WRN Rx Error Counter. This status bit indicates when repetitive errors are occurring during messages reception. A
read clears RX_WRN.
0 No such occurrence.
1 RXECTR 96.
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