Fast Ethernet Controller (FEC)
PXN20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor 25-17
The MII_SPEED field must be programmed with a value to provide an MDC frequency of less than or
equal to 2.5 MHz to be compliant with the IEEE 802.3 MII specification. The MII_SPEED must be set to
a non-zero value in order to source a read or write management frame. After the management frame is
complete the MSCR register may optionally be set to zero to turn off the MDC. The MDC generated has
a 50% duty cycle except when MII_SPEED is changed during operation (change takes effect following
either a rising or falling edge of MDC).
If the system clock is 50 MHz, programming this register to 0x0000_0005 results in an MDC frequency
of 50 MHz × 1/20 = 2.5 MHz. A table showing optimum values for MII_SPEED as a function of system
clock frequency is provided in Table 25-11.
Offset: FEC_BASE + 0x0044 Access: User read/write
0123456789101112131415
R0 000000000000000
W
Reset0000000000000000
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R00000000DIS_
PREA
MBLE
MII_SPEED
0
W
Reset0000000000000000
Figure 25-8. MII Speed Control Register (MSCR)
Table 25-10. MSCR Field Descriptions
Field Description
0–23 Reserved, should be cleared.
DIS_PREAMBLE Asserting this bit causes preamble (32 1’s) not to be prepended to the MII management frame. The MII
standard allows the preamble to be dropped if the attached PHY devices does not require it.
MII_SPEED MII_SPEED controls the frequency of the MII management interface clock (FEC_MDC) relative to the
system clock. A value of 0 in this field “turns off” the MDC and leaves it in low voltage state. Any non-zero
value results in the MDC frequency of 1/(MII_SPEED * 4) of the system clock frequency.
31 Reserved, should be cleared.
Table 25-11. Programming Examples for MSCR
System Clock Frequency MII_SPEED (field in reg) MDC frequency
50 MHz 0x5 2.5 MHz
66 MHz 0x7 2.36 MHz
80 MHz 0x8 2.5 MHz
100 MHz 0xA 2.5 MHz
132 MHz
1
0xD 2.5 MHz
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