Frequency Modulated Phase-Locked Loop (FMPLL)
PXN20 Microcontroller Reference Manual, Rev. 1
7-6 Freescale Semiconductor
Offset: FMPLL_BASE_ADDR + 0x0008 Access: User read/write
0 123456789101112131415
R 1
CLKCFG[0:2]
0 0 0 0 0 0 0 0
EPREDIV
W
Reset1 000000000000000
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R 0 0 0 0 0 0 0 0
EMFD
W
Reset0 00000000011000
Figure 7-3. FMPLL Enhanced Synthesizer Control Register 1 (ESYNCR1)
Table 7-4. ESYNCR1 Register Field Descriptions
Field Description
bit 0 Reserved.
Note: This bit is set to 1 on reset and always reads as 1.
CLKCFG Clock Configuration. The CLKCFG[0:2] bits are writable versions of the MODE, PLLSEL, and PLLREF bits
in the SYNSR. These change the clock mode, after reset has negated, via software. CLKCFG[0:2] map
directly to MODE, PLLSEL, and PLLREF to control the system clock mode (see Table 7- 3).
Note: CLKCFG[0:2] = 0b101 can produce an unpredictable clock output.
Note: The ESYNCR2[LOLRE] and ESYNCR2[LOCRE] should be set to 0 before changing the PLL mode, so
that a reset is not immediately generated when CLKCFG[0:2] is written.
EPREDIV Enhanced Pre-Divider. The EPREDIV bits control the value of the divider on the input clock. The output of
the pre-divider circuit generates the reference clock to the PLL analog loop. The decimal equivalent of the
EPREDIV binary number is substituted into the equation from Table 7- 10.
Note: Setting EPREDIV to any of the invalid states in Tabl e 7- 4 causes the PLL to produce an unpredictable
output clock. The output frequency of the divider must equal f
pllref
(see the PXN20 Microcontroller Data
Sheet).
When the EPREDIV bits are changed, the PLL immediately loses lock. If the EPREDIV bits are changed
during FM calibration, the current calibration sequence is terminated and the DEPTH bits are cleared. The
PLL re-locks to the new EPREDIV value. Modulation must be re-enabled manually. To prevent an immediate
reset, clear the LOLRE bit before writing the EPREDIV bits. In PLL bypass mode, the EPREDIV bits have no
effect.
EMFD Enhanced Multiplication Factor Divider. The EMFD bits control the value of the divider in the PLL feedback
loop. The value specified by the EMFD bits establish the multiplication factor applied to the reference
frequency. The decimal equivalent of the EMFD binary number is substituted into the equation from
Ta bl e 7 -1 1 for F
sys
to determine the equivalent multiplication factor. The range of settings is
32 EMFD 132.
Note: EMFD values less than 32 and greater than 132 are invalid and cause the PLL to produce an
unpredictable clock output. The VCO frequency must be within the f
VCO
specification (see the PXN20
Microcontroller Data Sheet).
When the EMFD bits are changed, the PLL loses lock.If the EMFD bits are changed during FM calibration,
the current calibration sequence is terminated and the DEPTH bits are cleared. The PLL re-locks to the new
EMFD value and you must manually re-enable modulation. To prevent an immediate reset, clear the LOLRE
bit before writing the EMFD bits.
In PLL Off mode, the EMFD bits have no effect.
Ta bl e 7 -6 shows the available divide ratios.
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