IEEE 1149.1 Test Access Port Controller (JTAGC)
PXN20 Microcontroller Reference Manual, Rev. 1
35-14 Freescale Semiconductor
controller enters the update-IR state. It contains fields for controlling access to a resource, as well as
controlling single-step operation and exit from OnCE mode.
Although the OCMD is updated during the update-IR TAP controller state, the corresponding resource is
accessed in the DR scan sequence of the TAP controller, and as such, the update-DR state must be
transitioned through in order for an access to occur. In addition, the update-DR state must also be
transitioned through in order for the single-step and/or exit functionality to be performed, even though the
command appears to have no data resource requirement associated with it.
012 3 456789
R
R/W GO EX RS
W
Reset:000 0 000010
Figure 35-8. OnCE Command Register (OCMD)
Table 35-3. e200z0 and e200z6 OnCE Register Addressing
RS Register Selected
000 0000 – 000 0001 Reserved
000 0010 JTAG ID (read-only)
000 0011 – 000 1111 Reserved
001 0000 CPU Scan Register (CPUSCR)
001 0001 No Register Selected (Bypass)
001 0010 OnCE Control Register (OCR)
001 0011 – 001 1111 Reserved
010 0000 Instruction Address Compare 1 (IAC1)
010 0001 Instruction Address Compare 2 (IAC2)
010 0010 Instruction Address Compare 3 (IAC3)
010 0011 Instruction Address Compare 4 (IAC4)
010 0100 Data Address Compare 1 (DAC1)
010 0101 Data Address Compare 2 (DAC2)
010 0110 – 010 1011 Reserved
010 1100 Debug Counter Register (DBCNT)
1
010 1101 Debug PCFIFO (PCFIFO) (read-only)
1
010 1110 – 010 1111 Reserved
011 0000 Debug Status Register (DBSR)
011 0001 Debug Control Register 0 (DBCR0)
011 0010 Debug Control Register 1 (DBCR1)
011 0011 Debug Control Register 2 (DBCR2)
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