Nexus Development Interface (NDI)
PXN20 Microcontroller Reference Manual, Rev. 1
36-90 Freescale Semiconductor
Program Trace Synchronization Messages
A program trace direct/indirect branch with sync message is messaged via the auxiliary port (provided
program trace is enabled) for the following conditions (see Table 36-60):
• Initial program trace message upon the first direct/indirect branch after exit from system reset or
whenever program trace is enabled
• Upon direct/indirect branch after returning from a CPU low power state
• Upon direct/indirect branch after returning from debug mode
• Upon direct/indirect branch after occurrence of queue overrun (can be caused by any trace
message), provided program trace is enabled
• Upon direct/indirect branch after the periodic program trace counter has expired indicating 255
without-sync program trace messages have occurred since the last with-sync message occurred
• Upon direct/indirect branch after assertion of the event in (EVTI) pin if the EIC bits within the DC1
register have enabled this feature
• Upon direct/indirect branch after the sequential instruction counter has expired indicating 255
instructions have occurred between branches
• Upon direct/indirect branch after a BTM message was lost due to an attempted access to a secure
memory location.
• Upon direct/indirect branch after a BTM message was lost due to a collision entering the FIFO
between the BTM message and either a watchpoint message or an ownership trace message
If the Nexus2+ module is enabled at reset, a EVTI assertion initiates a program trace direct/indirect branch
with sync message (if program trace is enabled) upon the first direct/indirect branch. The format for
program trace direct/indirect branch with sync messages is as follows:
Figure 36-69. Direct/Indirect Branch with Sync Message Format
The formats for program trace direct/indirect branch with sync. messages and indirect branch history with
sync. messages are as follows
:
Figure 36-70. Indirect Branch History with Sync. Message Format
Exception conditions that result in program trace synchronization are summarized in Table 36-60.
MSB LSB
234
F-ADDR I-CNT SRC
4 bits
1
TCODE (001011 or 001100)
1–8 bits1–32 bits 6 bits
Max length = 50 bits; Min length = 12 bits
HIST
MSB LSB
234
F-ADDR I-CNT SRC
5
4 bits
1
TCODE (011101)
1–8 bits1–32 bits1–32 bits 6 bits
Max length = 82 bits; Min length = 13 bits
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