Nexus Development Interface (NDI)
PXN20 Microcontroller Reference Manual, Rev. 1
36-92 Freescale Semiconductor
Relative Addressing
The relative address feature is compliant with the IEEE-ISTO 5001-2003 standard recommendations, and
is designed to reduce the number of bits transmitted for addresses of indirect branch messages.
The address transmitted is relative to the target address of the instruction that triggered the previous
indirect branch (or sync) message. It is generated by XOR-ing the new address with the previous address,
and then using only the results up to the most significant 1 in the result. To recreate this address, an XOR
of the (most-significant 0-padded) message address with the previously decoded address gives the current
address.
Previous address (A1) = 0x0003_FC01, New address (A2) = 0x0003_F365
Figure 36-71. Relative Address Generation and Re-creation
Execution Mode Indication
In order for a development tool to properly interpret instruction count and history information, it must be
aware of the execution mode context of that information. VLE instructions are interpreted differently from
non-VLE instructions.
Program trace messages provide the execution mode status in the least significant bit of the reconstructed
address field. A value of ‘0’ indicates that preceding instruction count and history information should be
interpreted in a non-VLE context. A value of ‘1’ indicates that the preceding instruction count and history
information should be interpreted in a VLE context. Note that when a branch results in an execution mode
switch, the program trace message resulting from that branch indicates the previous execution state. The
new state is not signaled until the next program trace message.
In some cases, a Program Correlation Message is generated to indicate execution mode status.
Refer to Program Correlation Messages for more information on these cases.
Branch/Predicate Instruction History (HIST)
If DC[PTM] is set, BTM messaging uses the branch history format. The branch history (HIST) packet in
these messages provides a history of direct branch execution used for reconstructing the program flow.
This packet is implemented as a left-shifting shift register. The register is always pre-loaded with a value
Message Generation:
A1 = 0000 0000 0000 0011 1111 1100 0000 0001
A2 = 0000 0000 0000 0011 1111 0011 0110 0101
A1 A2 = 0000 0000 0000 0000 0000 1111 0110 0100
Address Message (M1) = 1111 0110 0100
Address Re-creation:
A1 M1 = A2
A1 = 0000 0000 0000 0011 1111 1100 0000 0001
M1 = 0000 0000 0000 0000 0000 1111 0110 0100
A2 = 0000 0000 0000 0011 1111 0011 0110 0101
To Next Page
Loading...
