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NXP Semiconductors PXN2020 - Page 1352

NXP Semiconductors PXN2020
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Memory Map
PXN20 Microcontroller Reference Manual, Rev. 1
A-94 Freescale Semiconductor
0x014C TFLG5—Timer 5 flag register R/W 0x0000_0000 22.3.2.5/22-7
0x0150 LDVAL6—Timer 6 load value register R/W 0x0000_0000 22.3.2.2/22-5
0x0154 CVAL6—Timer 6 current value register R/W 0x0000_0000 22.3.2.3/22-5
0x0158 TCTRL6—Timer 6 control register R/W 0x0000_0000 22.3.2.4/22-6
0x015C TFLG6—Timer 6 flag register R/W 0x0000_0000 22.3.2.5/22-7
0x0160 LDVAL7—Timer 7 load value register R/W 0x0000_0000 22.3.2.2/22-5
0x0164 CVAL7—Timer 7 current value register R/W 0x0000_0000 22.3.2.3/22-5
0x0168 TCTRL7—Timer 7 control register R/W 0x0000_0000 22.3.2.4/22-6
0x016C TFLG7—Timer 7 flag register R/W 0x0000_0000 22.3.2.5/22-7
0x0170 LDVAL8—Timer 8 load value register R/W 0x0000_0000 22.3.2.2/22-5
0x0174 CVAL8—Timer 8 current value register R/W 0x0000_0000 22.3.2.3/22-5
0x0178 TCTRL8—Timer 8 control register R/W 0x0000_0000 22.3.2.4/22-6
0x017C TFLG8—Timer 8 flag register R/W 0x0000_0000 22.3.2.5/22-7
0x0180–0x3FFF Reserved
0xFFFE_4000
eMIOS_A
Chapter 28, Enhanced Modular Input/Output Subsystem (eMIOS200)
0x0000 EMIOS_MCRModule configuration register R/W 0x0000_0000 28.3.2.1/28-9
0x0004 EMIOS_GFRGlobal flag register R 0x0000_0000 28.3.2.2/28-10
0x0008 EMIOS_OUDROutput update disable register R/W 0x0000_0000 28.3.2.3/28-11
0x000C EMIOS_UCDISStop (disable) channel register R/W 0x0000_0000 28.3.2.4/28-11
0x0010–0x001F Reserved
0x0020 EMIOS_CADR[0]Channel A data register R/W 0x0000_0000 28.3.2.5/28-12
0x0024 EMIOS_CBDR[0]Channel B data register R/W 0x0000_0000 28.3.2.6/28-12
0x0028 EMIOS_CCNTR[0]Channel counter register R 0x0000_0000 28.3.2.7/28-13
0x002C EMIOS_CCR[0]Channel control register R/W 0x0000_0000 28.3.2.8/28-14
0x0030 EMIOS_CSR[0]Channel status register R 0x0000_0000 28.3.2.9/28-19
0x0034 EMIOS_ALTA[0]Alternate A register R/W 0x0000_0000 28.3.2.10/28-19
0x0038–0x003F Reserved
0x0040 EMIOS_CADR[1]Channel A data register R/W 0x0000_0000 28.3.2.5/28-12
0x0044 EMIOS_CBDR[1]Channel B data register R/W 0x0000_0000 28.3.2.6/28-12
0x0048 EMIOS_CCNTR[1]Counter register R 0x0000_0000 28.3.2.7/28-13
0x004C EMIOS_CCR[1]Control register R/W 0x0000_0000 28.3.2.8/28-14
Table A-4. PXN20 Detailed Register Map (continued)
Address Offset
from Module Base
Register
Access
1
Reset Value
2
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