Frequency Modulated Phase-Locked Loop (FMPLL)
PXN20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor 7-17
cycles again to obtain the delta-frequency count. The counter runs only during the high phase of the
triangular modulation waveform. Several half-modulation periods are measured during the calibration
routine to increase the resolution of the frequency measurement. This results in a measurement of the
average frequency during the high phase of the modulation waveform, which under ideal circumstances is
equivalent to one-half of the desired modulation depth. When the reference counter has counted to the new
programmed number of reference count cycles, the feedback counter is stopped again.
The delta-frequency count minus the center frequency count (COUNT0) results in a delta count
proportional to the reference current into the modulation D/A. That delta count is subtracted from the
expected value for the selected depth resulting in an error count. The sign of this error count determines
the direction taken by the calibration D/A to update the calibration current. After obtaining the error count
for the present iteration, both counters are cleared. The stored count of COUNT0 is preserved while a new
feedback count is obtained, and the process to determine the error count is repeated. The calibration system
repeats this process eight times, once for each bit of the calibration D/A.
After the last decision is made, a 1 is written to the CALDONE bit of the SYNSR. If an error occurs during
the calibration routine, then CALPASS remains 0. If the routine completed successfully, CALPASS is set
to 1.
7.4.3.4.2 Programming System Clock Frequency With Frequency Modulation
The following steps illustrate proper programming of the frequency modulation mode. These steps ensure
proper operation of the calibration routine and prevent frequency overshoot from the sequence. The PLL
should be programmed and allowed to lock in non-FM mode at the desired frequency as outlined in
Section 7.4.3.3.5, Programming System Clock Frequency.
1. Monitor LOCK bit. Do not proceed until the PLL is locked in non-modulation mode.
2. Write a value of ERFD = ERFD + 1 to the ERFD field of the ESYNCR2 to ensure the maximum
system frequency is not exceeded during the calibration routine. This should have been done when
allowing the PLL to lock in non-FM mode.
3. Program the desired modulation rate and depth to the ERATE and EDEPTH bitfields
simultaneously using a single 32-bit write to the ESYNCR register2. Setting ERATE alone may set
the LOLF flag. This action initiates the calibration sequence.
4. Allow time for the calibration sequence. Wait for the PLL to lock (i.e.,the LOCK bit to set in the
SYNSR). At this time CALDONE should be asserted. CALPASS is asserted if the calibration was
successful. If not, the calibration can be re-initiated by repeating from step 3. When the PLL
achieves lock, write the ERFD value desired.
The frequency modulation system is dependent on several factors, including the accuracies of the
V
DDSYN
/V
SSSYN
voltage, of the crystal oscillator frequency, and of the manufacturing variation.
For example, if a 5% accurate supply voltage is used, then a 5% modulation depth error results. If the
crystal oscillator frequency is skewed from the nominal operating frequency, the resulting modulation
frequency is proportionally skewed. Finally, the error due to the manufacturing and environment variation
alone can cause the frequency modulation depth error to be greater than 20%.
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