NXP Semiconductors PXN2020 - Page 187

System Integration Unit (SIU)
PXN20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor 8-5
0x002C SIU_IFEER—External IRQ falling-edge event enable register R/W 0x0000_0000 8.3.2.10/8-20
0x0030 SIU_IDFR—External IRQ digital filter register R/W 0x0000_0000 8.3.2.11/8-21
0x0034 SIU_IFIR—External IRQ filtered input register R/W 0x0000_0000 8.3.2.12/8-22
0x0038–0x003F Reserved
0x0040–0x0174 SIU_PCR0 – SIU_PCR154—Pad configuration register 0 – Pad
configuration register 154
R/W —
1
8.3.2.13/8-22
0x0176–0x060F Reserved
0x0610–0x0689
SIU_GPDO16_19 – SIU_GPDO152_154—GPIO pin data output
register 16-19–GPIO pin data output register 152–154
R/W 0x0000_0000 8.3.2.14/8-26
0x0690–0x07FF Reserved
0x0800–0x0898 SIU_GPDI0_3 – SIU_GPDI152_155—GPIO pin data input
register 0–3 –GPIO pin data input register 152–154
R/W —
1
8.3.2.15/8-28
0x089C–0x0903 Reserved
0x0904 SIU_ISEL1—External interrupt select register 1 R/W 0x0000_0000 8.3.2.16/8-29
0x0908 SIU_ISEL2—External interrupt select register 2 R/W 0x0000_0000 8.3.2.17/8-33
0x090C–0x090F Reserved
0x0910 SIU_ISEL4—ADC trigger input select register 4 R/W 0x0000_0000 8.3.2.18/8-35
0x0914–0x097F Reserved
0x0980 SIU_CCR—Chip configuration register R/W 0x000U_0000 8.3.2.19/8-36
0x0984 SIU_ECCR—External clock control register R/W 0x0000_1001 8.3.2.20/8-37
0x0988 SIU_GPR0—General purpose register 0 R/W 0x0000_0000 8.3.2.21/8-38
0x098C SIU_GPR1—General purpose register 1 R/W 0x0000_0000 8.3.2.21/8-38
0x0990 SIU_GPR2—General purpose register 2 R/W 0x0000_0000 8.3.2.21/8-38
0x0994 SIU_GPR3—General purpose register 3 R/W 0x0000_0000 8.3.2.21/8-38
0x0998–0x099F Reserved
0x09A0 SIU_SYSCLK—System clock register R/W 0x0000_0000 8.3.2.22/8-38
0x09A4 SIU_HLT0—Halt request register 0 R/W 0x0000_0000 8.3.2.23/8-39
0x09A8 SIU_HLT1—Halt request register 1 R/W 0x0000_0000 8.3.2.23/8-39
0x09AC SIU_HLTACK0—Halt acknowledge register 0 R 0x0000_0000 8.3.2.24/8-41
0x09B0 SIU_HLTACK1—Halt acknowledge register 1 R 0x0000_0000 8.3.2.24/8-41
0x09B4 SIU_EMIOS_SEL0—eMIOS select register 0 R/W 0x0000_0000 8.3.2.25/8-44
0x09B8 SIU_EMIOS_SEL1—eMIOS select register 1 R/W 0x0000_0000 8.3.2.25/8-44
0x09BC SIU_EMIOS_SEL2—eMIOS select register 2 R/W 0x0000_0000 8.3.2.25/8-44
Table 8-1. SIU Memory Map (continued)
Offset from
SIU_BASE
(0xFFFE_8000)
Register Access Reset Value Section/Page