System Integration Unit (SIU)
PXN20 Microcontroller Reference Manual, Rev. 1
8-40 Freescale Semiconductor
Offset: SIU_BASE + 0x09A4 Access: User read-only
0
1
1
1
2
1
3
1
4
1
5
1
678
1
9 101112131415
R000000
HLT
6
HLT
7
0
HLT
9
HLT
10
HLT
11
HLT
12
HLT
13
HLT
14
HLT
15
W
Reset0000000000000000
16 17 18 19 20 21 22 23 24
1
25
1
26 27 28 29 30
1
31
R
HLT
16
HLT
17
HLT
18
HLT
19
HLT
20
HLT
21
HLT
22
HLT
23
00
HLT
26
HLT
27
HLT
28
HLT
29
0
HLT
31
W
Reset0000000000000000
1
Writes to this bit are reflected in the SIU_HLT0 and SIU_HLTACK0 register, but have no other effect.
Figure 8-26. Halt Register 0 (SIU_HLT0)
Table 8-27. SIU_HLT0 Register Field Descriptions
Field Description
HLT6 Halt bit 6. Setting this bit halts the EMIOS200 module.
HLT7 Halt bit 7. Setting this bit halts the PIT module.
HLT9 Halt bit 9. Setting this bit halts the CTU module.
HLT10 Halt bit 10. Setting this bit halts the FLEXCAN_F module.
HLT11 Halt bit 11. Setting this bit halts the FLEXCAN_E module.
HLT12 Halt bit 12. Setting this bit halts the FLEXCAN_D module.
HLT13 Halt bit 13. Setting this bit halts the FLEXCAN_C module.
HLT14 Halt bit 14. Setting this bit halts the FLEXCAN_B module.
HLT15 Halt bit 15. Setting this bit halts the FLEXCAN_A module.
HLT16 Halt bit 16. Setting this bit halts the ESCI_H module.
HLT17 Halt bit 17. Setting this bit halts the ESCI_G module.
HLT18 Halt bit 18. Setting this bit halts the ESCI_F module.
HLT19 Halt bit 19. Setting this bit halts the ESCI_E module.
HLT20 Halt bit 20. Setting this bit halts the ESCI_D module.
HLT21 Halt bit 21. Setting this bit halts the ESCI_C module.
HLT22 Halt bit 22. Setting this bit halts the ESCI_B module.
HLT23 Halt bit 23. Setting this bit halts the ESCI_A module.
HLT26 Halt bit 26. Setting this bit halts the DSPI_B module.
HLT27 Halt bit 27. Setting this bit halts the DSPI_A module.
HLT28 Halt bit 28. Setting this bit halts the I
2
C_B module.
HLT29 Halt bit 29. Setting this bit halts the I
2
C_A module.
HLT31 Halt bit 31. Setting this bit halts the ADC module.
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