NXP Semiconductors PXN2020 - Page 421

Semaphores
PXN20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor 15-9
reset mechanism requires two consecutive writes with predefined data patterns from the same processor
to force the clearing of the IRQ notification(s). The required access pattern is:
1. A processor performs a 16-bit write to the SEMA4_RSTNTF memory location. The most
significant byte (SEMA4_RSTNTF[RSTNDP]) must be 0x47; the least significant byte is a “don’t
care” for this reference.
2. The same processor performs a second 16-bit write to the SEMA4_RSTNTF location. For this
write, the upper byte (SEMA4_RSTNTF[RSTNDP]) is the logical complement of the first data
pattern (0xb8) and the lower byte (SEMA4_RSTNTF[RSTNTN]) specifies the notification(s) to
be reset. This field can specify a single notification be cleared or that all notifications are cleared.
3. Reads of the SEMA4_RSTNTF location return information on the 2-bit state machine
(SEMA4_RSTNTF[RSTNSM]) that implements this function, the bus master performing the reset
(SEMA4_RSTNTF[RSTNMS]) and the notification number(s) last cleared
(SEMA4_RSTNTF[RSTNTN]). Reads of the SEMA4_RSTNTF register do not affect the secure
reset finite state machine in any manner.
Figure 15-6. Semaphores (Secure) Reset IRQ Notification (SEMA4_RSTNTF)
Offset: SEMA4_BASE + 0x0104 (SEMA4_RSTNTF) Access: User read/write
0123456789101112131415
R 0 0 RSTNSM 0 RSTNMS
RSTNTN
W RSTNDP
Reset0000000000000000