Software Watchdog Timer (SWT)
PXN20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor 20-9
to open due to synchronization logic in the watchdog design. This delay could be as many as 3 system plus
4 counter clock cycles.
The interrupt then reset bit (SWT_CR[ITR]) controls the action taken when a time-out occurs. If the
SWT_CR[ITR] bit is not set, a reset is generated immediately on a time-out. If the SWT_CR[ITR] bit is
set, an initial time-out causes the SWT to generate an interrupt and load the down counter with the time-out
period. If the service sequence is not written before the second consecutive time-out, the SWT generates
a system reset. The interrupt is indicated by the time-out interrupt flag (SWT_IR[TIF]). The interrupt
request is cleared by writing a one to the SWT_IR[TIF] bit.
The SWT_CO register shows the value of the down counter when the watchdog is disabled. When the
watchdog is enabled this register is cleared. The value shown in this register can lag behind the value in
the internal counter for as many as 6 system plus 8 counter clock cycles.
The SWT_CO can be used during a software self test of the SWT. For example, the SWT can be enabled
and not serviced for a fixed period of time less than the time-out value. Then the SWT can be disabled
(SWT_CR[WEN] cleared) and the value of the SWT_CO read to determine if the internal down counter
is working properly.
To Next Page
Loading...
