FlexRay Communication Controller (FlexRAY)
PXN20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor 26-3
Figure 26-1. FlexRay Block Diagram
The protocol engine has two transmitter units TxA and TxB and two receiver units RxA and RxB for
sending and receiving frames through the two FlexRay channels. The time control unit (TCU) is
responsible for maintaining global clock synchronization to the FlexRay network. The overall activity of
the PE is controlled by the sequencer engine (SEQ).
The controller host interface provides host access to the module’s configuration, control, and status
registers, as well as to the message buffer configuration, control, and status registers. The message buffers
themselves, which contain the frame header and payload data received or to be transmitted, and the slot
status information, are stored in the FlexRay memory.
The clock domain crossing unit implements signal crossing from the CHI clock domain to the PE clock
domain and vice versa, to allow for asynchronous PE and CHI clock domains.
The controller stores the frame header and payload data of frames received or of frames to be transmitted
in the FlexRay memory. The application accesses the FlexRay memory to retrieve and provide the frames
to be processed by the controller. In addition to the frame header and payload data, the controller stores
the synchronization frame related tables in the FlexRay memory for application processing.
The FlexRay memory is located in the system memory of the MCU. The controller has access to the
FlexRay memory via its bus master interface (BMIF). The host provides the start address of the FlexRay
memory window within the system memory by programming the System Memory Base Address Register
(SYMBADR). All FlexRay memory related offsets are stored in offset registers. The physical address
pointer into the FlexRay memory window of the MCU system memory is calculated using the offset values
the FlexRay memory base address.
Clock Domain Crossing
PE
TxA
RxA
TCU
config
SEQ
CHI
HIF
SEARCH
LUT
BCU
FR_A_RX
FR_B_RX
FR_DBG[0]
FR_A_TX
FR_A_TX_EN
FR_B_TX
FR_B_TX_EN
FR_DBG[1]
FR_DBG[2]
FR_DBG[3]
FlexRay
Peripheral
Bridge B
System
Memory
BMIF
System Bus
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