FlexRay Communication Controller (FlexRAY)
PXN20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor 26-77
NOTE
If a message buffer is assigned to the last slot in a FlexyRay communication
cycle and a system memory access timeout or illegal address access occurs
during the system memory access in this slot, it is possible that for all future
communication required:
• No slot status information will be written,
• The message buffer status will not be updated, and
• No message frames will be received. If this happens, several message
buffers can never be locked by the application.
However, if this occurs, either the System Bus Communication Failure
Error Flag (SBCF_EF) or the Illegal System Bus Address Error Flag
(ILSA_EF) will be set in the Controller Host Interface Error Flag Register
(CHIERFR).
The FlexRay module and the system memory subsystem should be
configured to avoid the occurrence of system memory access timeouts and
illegal address accesses. In case, one of the error flags
CHIERFR[SBCF_EF] or CHIERFR[ILSA_EF] is set, the application
should stop the FlexRay controller via a FREEZE or HALT command and
subsequently restart the controller.
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