NXP Semiconductors PXN2020 - Page 729

FlexRay Communication Controller (FlexRAY)
PXN20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor 26-115
Figure 26-131. Double Transmit Message Buffer Access Regions Layout
The trigger bits MBCCSRn[EDT] and MBCCSRn[LCKT], and the interrupt enable bit
MBCCSRn[MBIE] are not under access control and can be accessed from the application at any time. The
status bits MBCCSRn[EDS] and MBCCSRn[LCKS] are not under access control and can be accessed
from the controller at any time.
The interrupt flag MBCCSRn.MBIF is not under access control and can be accessed from the application
and the controller at any time. controller set access has higher priority.
The controller restricts its access to the regions, depending on the current state of the corresponding part
of the double transmit message buffer. The application must adhere to these restrictions in order to ensure
data consistency. The states for the commit side of a double transmit message buffer are given in
Figure 26-132. A description of the states is given in Table 26-108. The states for the transmit side of a
Table 26-106. Double Transmit Message Buffer Access Regions Description
Access Description
Region
Type
Application Module
Commit Side
CFG read/write — Message Buffer Configuration
MSG read/write — Message Buffer Data and Control access
ITX — read/write Internal Message Transfer.
SS — write-only Slot Status Update
Transmit Side
CFG read/write — Message Buffer Configuration
SR — read-only Message Buffer Search
TX — read-only Internal Message Transfer, Message Transmission
SS — write-only Slot Status Update
Message Buffer Data Field: DATA[0-N]
Message Buffer Header Field: Frame Header
MBCCSR(2n)[CMT]
Message Buffer Header Field: Slot Status
Message Buffer Header Field: Data Field Offset
MBCCFR(2n)[MTM/CHA/CHB/CCF*]
MBFIDR(2n)[FID]
MBIDXR(2n)[MBIDX]
MBCCSR(2n)[MBT/MTD]
Message Buffer Data Field: DATA[0-N]
Message Buffer Header Field: Frame Header
MBCCSR(2n+1)[CMT]
Message Buffer Header Field: Slot Status
Message Buffer Header Field: Data Field Offset
MBCCFR(2n+1)[MTM/CHA/CHB/CCF*]
MBFIDR(2n+1)[FID]
MBIDXR(2n+1)]MBIDX]
MBCCSR(2n+1)[MBT/MTD]
Commit Side Transmit Side
CFG
MSG
CFG
ITX
SS
SS
SR
TX