Media Local Bus (MLB)
PXN20 Microcontroller Reference Manual, Rev. 1
27-34 Freescale Semiconductor
• The CCBCRn[BCA] field is loaded into an internal hardware register (not visible to system
software) at the start of each incoming asynchronous or control RX packet. If the packet is later
aborted (caused by AsyncBreak, ControlBreak, ReceiverBreak, or ReceiverProtocolError),
CCBCRn[BCA] is restored with the address pointer in the internal hardware register. The next
packet then overwrites the aborted RX packet, as aborted RX packets are not stored in system
memory. (See Note 3 in Figure 27-19).
• During the processing of the Current Buffer, CCBCRn[BCA] continues to mark which quadlet of
the asynchronous or control RX packet is currently being processed. (See Note 4 in Figure 27-19).
• Software is unable to predict the buffer length for asynchronous and control RX channels, since the
length of each RX packet is defined by the packet header (PML) and extracted by hardware as the
packet is received. As a result, there is a possibility that the last packet in the Current Buffer may
extend beyond CCBCRn[BFA]. System memory must accommodate this by allowing the buffers
to overflow by the worst-case packet length. (See Note 5A in Figure 27-19).
•A Buffer Done interrupt is generated (CSCRn[STS[2]] set) when the last quadlet from the last
packet (in the Current Buffer) has been successfully received. Software may then begin processing
the buffer. (See Note 6 in Figure 27-19).
NOTE
When the DMA Controller encounters an asynchronous or control packet
that is broken (or has an error), CCBCRn[BCA] is reloaded with the start
address of the last packet and the broken packet is overwritten. This
mechanism ensures that system software can always calculate the address of
the next packet start address within system memory.
Single-packet buffering of asynchronous and control RX packets should be handled in the same manner
described for multi-packet buffering, with the exception that the beginning and end address of the
Next Buffer should be set to the same address (e.g. CNBCRn[BSA] = CNBCRn[BEA]).
27.4.6.1.2 Packet Transmission
When multi-packet buffering is used for transmitting asynchronous or control data packets, buffer
processing should be handled in the following manner:
• At the start of buffer processing, the beginning of the Next Buffer becomes the beginning of the
Current Buffer
, as CNBCRn[BSA] is loaded into CCBCRn[BCA]. Additionally, the end of the
Next Buffer becomes the end of the Current Buffer, as CNBCRn[BEA] is loaded into
CCBCRn[BFA]. (See Note 1 in Figure 27-19).
•A Buffer Start interrupt is generated (CSCRn[STS[3]] set), which informs software that hardware
has updated CCBCRn, cleared the local channel CSCRn[RDY] bit, and is available to accept the
next buffer. Software may then prepare the Next Buffer by writing: CNBCRn[BSA],
CNBCRn[BEA], and CSCRn[RDY]. (See Note 2 in Figure 27-19).
• During the processing of the Current Buffer, CCBCRn[BCA] continues to mark which quadlet of
the asynchronous or control TX packet is currently being processed. (See Note 4 in Figure 27-19).
• System software can determine the exact buffer length for TX channels. As a result, the last packet
in the Current Buffer should coincide with CCBCRn[BFA]. (See Note 5B in Figure 27-19).
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