Enhanced Modular Input/Output Subsystem (eMIOS200)
PXN20 Microcontroller Reference Manual, Rev. 1
28-16 Freescale Semiconductor
FORCMB Force Match B Bit. For output modes, the FORCMB bit is equivalent to a successful comparison on
comparator B (except that the FLAG bit is not set). This bit is cleared by reset and is always read as 0. This
bit is valid for every output operation mode which uses comparator B, otherwise it has no effect.
0 Has no effect.
1 Force a match at comparator B.
For input modes, the FORCMB bit is not used and writing to it has no effect.
BSL Bus Select Bits. The BSL bits are used to select either one of the counter buses or the internal counter to be
used by the unified channel.
EDSEL Edge Selection Bit. For input modes, the EDSEL bit selects if the internal counter is triggered by both edges
of a pulse or by a single edge only as defined by the EDPOL bit. When not shown in the mode of operation
description, this bit has no effect.
0 Single edge triggering defined by the EDPOL bit.
1 Both edges triggering.
For GPIO in mode, the EDSEL bit selects if a FLAG can be generated.
0 A FLAG is generated as defined by the EDPOL bit.
1 No FLAG is generated.
For SAOC mode, the EDSEL bit selects the behavior of the output flip-flop at each match.
0 The EDPOL value is transferred to the output flip-flop.
1 The output flip-flop is toggled.
EDPOL Edge Polarity Bit. For input modes, the EDPOL bit asserts which edge triggers either the internal counter or
an input capture or a FLAG. When not shown in the mode of operation description, this bit has no effect.
0 Trigger on a falling edge.
1 Trigger on a rising edge.
For output modes, the EDPOL bit is used to select the logic level on the output pin.
0 A match on comparator A clears the output flip-flop, while a match on comparator B sets it.
1 A match on comparator A sets the output flip-flop, while a match on comparator B clears it.
MODE[0:6] Mode Selection Bits. The MODE bits select the mode of operation of the unified channel, as shown in
Ta bl e 2 8- 11. Refer to Table 28-1 for more information on the different modes.
Note: If a reserved value is written to MODE, the results are unpredictable.
Table 28-10. EMIOS_CCR[n] Field Descriptions (continued)
Field Description
BSL Selected Bus
00 All channels: counter bus[A]
01 Channels 0 to 7: counter bus[B]
Channels 8 to 15: counter bus[C]
Channels 16 to 23: counter bus[D]
Channels 24 to 31: counter bus[E]
10
Reserved
11 All channels: internal counter
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