NXP Semiconductors PXN2020 - Page 857

Enhanced Modular Input/Output Subsystem (eMIOS200)
PXN20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor 28-35
Figure 28-31. Quadrature Decode Mode Example with Count & Direction Encoder
Figure 28-32. Quadrature Decode Mode Example with Phase_A & Phase_B Encoder
28.4.1.1.10 Modulus Counter (MC) Mode
The MC mode can be used to provide a time base for a counter bus or as a general purpose timer.
MODE[6] bit selects internal or external clock source when cleared or set, respectively. When external
clock is selected, the input signal pin is used as the source and the triggering polarity edge is selected by
the EDPOL and EDSEL in the EMIOS_CCR[n] register.
The internal counter counts up from the current value until it matches the value in register A1. Register B1
is cleared and is not accessible to the MCU. The MODE[4] bit selects up mode or up/down mode, when
cleared or set, respectively.
When in up count mode, a match between the internal counter and register A1 sets the FLAG and clears
the internal counter. The timing of those events varies according to the MC mode setup as follows:
Notes: EMIOS_CADR[n]  A1
+
1
+
1
+
1
+
1
+
1
+
1
+
1
-1 -1 -1 -1 -1
EMIOS_CCNTR[n] inc/dec
Direction (from UC[n])
Count (from UC[n –1])
0x000000
EMIOS_CCNTR[n]
Time
A1 Write
A1 Match
FLAG Pin/Register
A1 Match
Value 1
(Value 1)
MODE[6] = 0
EDPOL = 1
+
1
Notes: EMIOS_CADR[n] = A1
+
1
+
1
+
1
+
1
+
1
+
1
+
1
+
1
-1 -1 -1 -1 -1
+
1
+
1
+
1
+
1
+
1
+
1
-1
EMIOS_CCNTR[n] inc/dec
Phase A (from UC[n])
Phase B (from UC[n –1])
0x000000
EMIOS_CCNTR[n]
Time
A1 Write
A1 Match
FLAG Pin/Register
A1 Match A1 Match A1 Match A1 Match
A1 Write
Value 2
Value 1
(Value 1) (Value 2)
-1
+
1
+
1
-1 -1 -1 -1 -1
+
1
+
1
+
1
+
1
+
1
+
1
-1
-1
+
1
MODE[6] = 0