Enhanced Modular Input/Output Subsystem (eMIOS200)
PXN20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor 28-41
Figure 28-39. OPWFMB A1 and B1 Match to Output Register Delay
Figure 28-40 shows the generated output signal if A1 is set to zero. Because the counter does not reach
zero in this mode, the channel internal logic infers a match as if A1 = 0x00_0001 with the difference that
in this case, the posedge of the match signal is used to trigger the output pin transition instead of the
negedge used when A1 = 0x00_0001. A1 posedge match signal from cycle (n + 1) occurs at the same time
as B1 negedge match signal from cycle (n). This allows using the A1 posedge match to mask the B1
negedge match when they occur at the same time. The result is that no transition occurs on the output
flip-flop and a 0% duty cycle is generated.
8
1
4
A1 Match
5
A1 Value 0x000004
A1 Match
A1 Match Negedge
Output Pin
EMIOS_CCNTR
Time
B1 Match
B1 Match
B1 Match Negedge
B1 Value 0x000008
System Clock
Prescaler
Detection
Detection
Negedge
Detection
Negedge
Detection
EDPOL = 0
To Next Page
Loading...
