Controller Area Network (FlexCAN)
PXN20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor 29-15
in freeze mode. Exceptions are the BOFF_MSK, ERR_MSK, TWRN_MSK, RWRN_MSK, and
BOFF_REC bits, which can be accessed at any time.
Offset: Base + 0x0004 Access: User read/write
0 1 2 3 4 5 6 7 8 9 101112131415
R
PRESDIV RJW PSEG1 PSEG2
W
Reset0 0 0 0 0 0 0 0 0 0000000
16 17v 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
BOFF
_MSK
ERR_
MSK
CLK_
SRC
LPB
TWRN
_ MSK
RWRN
_MSK
00
SMP
BOFF
_REC
TSYN
LBUF LOM PROPSEG
W
Reset0 0 0 0 0 0 0 0 0 0000000
Figure 29-6. Control Register (CANx_CTRL)
Table 29-8. CANx_CTRL Field Descriptions
Bits Description
PRESDIV Prescaler Division Factor. Defines the ratio between the CPI clock frequency and the serial clock (SCK)
frequency. The SCK period defines the time quantum of the CAN protocol. For the reset value, the SCK
frequency is equal to the CPI clock frequency. The maximum value of this register is 0xFF, that gives a minimum
SCK frequency equal to the CPI clock frequency divided by 256. For more information, refer to Section 29.4.7.4,
Protocol Timing.
RJW Resync Jump Width. Defines the maximum number of time quanta that a bit time can be changed by one
re-synchronization. One time quantum is equal to one SCK period. The valid programmable values are 0–3.
PSEG Phase Segment 1. Defines the length of phase buffer segment 1 in the bit time. The valid programmable values
are 0–7.
PSEG2 Phase Segment 2. Defines the length of phase buffer segment 2 in the bit time. The valid programmable values
are 1–7.
BOFF_MSK Bus Off Mask. Provides a mask for the bus off interrupt.
0 Bus off interrupt disabled.
1 Bus off interrupt enabled.
ERR_MSK Error Mask. Provides a mask for the error interrupt.
0 Error interrupt disabled.
1 Error interrupt enabled.
S-clock frequency
CPI clock frequency
PRESDIV 1+
-----------------------------------------------------=
Resync Jump Width RJW + 1=
Phase Buffer Segment 1 PSEG1 + 1Time Quanta=
Phase Buffer Segment 2 PSEG2 + 1Time Quanta=
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