Controller Area Network (FlexCAN)
PXN20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor 29-19
CANx_RXGMASK also applies to all elements of the ID filter table, except elements 6-7, which have
individual masks.
The contents of this register must be programmed while the module is in Freeze Mode, and must not be
modified when the module is transmitting or receiving frames.
29.3.4.4.2 Rx 14 Mask (CANx_RX14MASK)
This register is provided for legacy support. On the PXN20, setting the BCC bit in CANx_MCR causes
the CANx_RX14MASK register to have no effect on the module operation.
CANx_RX14MASK is used as acceptance mask for the Identifier in Message Buffer 14. When the FEN
bit in CANx_MCR is set (FIFO enabled), the CANx_RX14MASK also applies to element 6 of the ID filter
table. This register has the same structure as the Rx Global Mask Register. It must be programmed while
the module is in freeze mode, and must not be modified when the module is transmitting or receiving
frames.
• Address Offset: 0x14
• Reset Value: 0xFFFF_FFFF
29.3.4.4.3 Rx 15 Mask (CANx_RX15MASK)
This register is provided for legacy support. On the PXN20, setting the BCC bit in CANx_MCR causes
the CANx_RX15MASK register to have no effect on the module operation.
When the BCC bit is negated, CANx_RX15MASK is used as acceptance mask for the Identifier in
Message Buffer 15. When the FEN bit in CANx_MCR is set (FIFO enabled), the CANx_RX14MASK also
applies to element 7 of the ID filter table. This register has the same structure as the Rx Global Mask
Register. It must be programmed while the module is in freeze mode, and must not be modified when the
module is transmitting or receiving frames.
Offset: Base + 0x0010 Access: User read/write
0123456789101112131415
R
MI31 MI30 MI29 MI28 MI27 MI26 MI25 MI24 MI23 MI22 MI21 MI20 MI19 MI18 MI17 MI16
W
Reset1111111111111111
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
MI15 MI14 MI13 MI12 MI11 MI10 MI9 MI8 MI7 MI6 MI5 MI4 MI3 MI2 MI1 MI0
W
Reset1111111111111111
Figure 29-8. Rx Mask Register (CANx_RXGMASK)
Table 29-10. CANx_RXGMASK Field Descriptions
Field Description
MIn Mask Bits. For normal Rx MBs, the mask bits affect the ID filter programmed on the MB. For the Rx FIFO, the
mask bits affect all bits programmed in the filter table (ID, IDE, RTR).
0 the corresponding bit in the filter is “don’t care.”
1 The corresponding bit in the filter is checked against the one received.
To Next Page
Loading...
