Enhanced Serial Communication Interface (eSCI)
PXN20 Microcontroller Reference Manual, Rev. 1
31-2 Freescale Semiconductor
• 13-bit baud rate selection
• Programmable frame, payload, and character format
• Support of 2 stop bits in receiver path
• Hardware parity generation and checking
— Programmable even or odd parity
• Programmable polarity of RXD pin
• Separately enabled transmitter and receiver
• Two receiver wake up methods:
— Idle line wake-up
— Address mark wake-up
• Interrupt-driven operation with eight flags:
— Transmitter empty
— Transmission complete
— Receiver full
— Idle receiver input
— Receiver overrun
— Noise error
— Framing error
— Parity error
• Receiver framing error detection
• 1/16 bit-time noise detection
• 2 channel DMA interface
• LIN support
— LIN Master Node functionality (master and slave task)
— Compatible with LIN slaves from revisions 1.x and 2.0 of the LIN standard
— Detection of Bit Errors, Physical Bus Errors, and Checksum Errors
— All status bit can generate maskable interrupts
— Application layer CRC support
— Programmable CRC polynom
— Detection and generation of wakeup characters
— Programmable wakeup delimiter time
— Programmable slave timeout
— Can be configured to include header bits in checksum
— LIN DMA interface
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