ST STM8S

Clock control (CLK) RM0016
100/449 Doc ID 14587 Rev 8
9.10 CLK register map and reset values
Table 19. CLK register map and reset values
Address
offset
Register name76543210
0x00
CLK_ICKR
Reset value
-
0
-
0
REGAH
0
LSIRDY
0
LSIEN
0
FHWU
0
HSIRDY
0
HSIEN
1
0x01
CLK_ECKR
Reset value
-
0
-
0
-
0
-
0
-
0
-
0
HSERDY
0
HSEEN
0
0x02 Reserved area (1 byte)
0x03
CLK_CMSR
Reset value
CKM7
1
CKM6
1
CKM5
1
CKM4
0
CKM3
0
CKM2
0
CKM1
0
CKM0
1
0x04
CLK_SWR
Reset value
SWI7
1
SWI6
1
SWI5
1
SWI4
0
SWI3
0
SWI2
0
SWI1
0
SWI0
1
0x05
CLK_SWCR
Reset value
-
x
-
x
-
x
-
x
SWIF
x
SWIEN
x
SWEN
x
SWBSY
x
0x06
CLK_CKDIVR
Reset value
-
0
-
0
-
0
HSIDIV1
1
HSIDIV0
1
CPUDIV2
0
CPUDIV12
0
CPUDIV0
0
0x07
CLK_PCKENR1
Reset value
PCKEN17
1
PCKEN16
1
PCKEN15
1
PCKEN14
1
PCKEN13
1
PCKEN12
1
PCKEN11
1
PCKEN10
1
0x08
CLK_CSSR
Reset value
-
0
-
0
-
0
-
0
CSSD
0
CSSDIE
0
AUX
0
CSSEN
0
0x09
CLK_CCOR
Reset value
-
0
CCOBSY
0
CCORDY
0
CCOSEL3
0
CCOSEL2
0
CCOSEL1
0
CCOSEL0
0
CCOEN
0
0x0A
CLK_PCKENR2
Reset value
PCKEN27
1
PCKEN26
1
PCKEN25
1
PCKEN24
1
PCKEN23
1
PCKEN22
1
PCKEN21
1
PCKEN20
1
0x0B Reserved area (1 byte)
0x0C
CLK_HSITRIMR
Reset value
-
0
-
0
-
0
-
0
-
0
HSITRIM2
0
HSITRIM1
0
HSITRIM0
0
0x0D
CLK_SWIMCCR
Reset value
-
x
-
x
-
x
-
x
-
x
-
x
-
x
SWIMCLK
0