ST STM8S

Clock control (CLK) RM0016
78/449 Doc ID 14587 Rev 8
Figure 20. Clock tree
1. Legend: HSE = High speed external clock signal; HSI = High speed internal clock signal; LSI = Low Speed internal clock
signal.
HSE OSC
1-24MHz
OSCIN
OSCOUT
HSI RC
16 MHz
LSI RC
128 kHz
/1
/2
/4
/8
fMASTER
fHSE
fHSIDIV
fLSI
HSIDIV[1:0]
/1
/2
/4
/8
/16
/32
/64
/128
CPUDIV[2:0]
fCPU
CKM[7:0]
to Timers
Peripheral clock
To CPU and
To independent watchdog
window watchdog
I2C
SPI
ADC
AWU
CAN
CCO
fHSI
fHSIDIV
fHSE
fLSI
fMASTER
fCPU
fCPU/2
fCPU/4
fCPU/8
fCPU/16
fCPU/32
fCPU/64
Configurable clock output
CCOSEL[3:0]
Master
Clock
Switch
enable (8 bits)
To auto wakeup unit (AWU)
HSE Ext.
EXTCLK OPT BIT
CKAWUSEL OPT BIT
128 kHz
PRSC(1:0) OPT BITS
fHSI
CSS
LSI_EN OPT BIT
UART