Clock control (CLK) RM0016
86/449 Doc ID 14587 Rev 8
9.5 Peripheral clock gating (PCG)
Gating the clock to unused peripherals helps reduce power consumption. Peripheral clock
Gating (PCG) mode allows you to selectively enable or disable the f
MASTER
clock
connection to the following peripherals at any time in Run mode:
● ADC
● I2C
● AWU (register clock, not counter clock)
● SPI
● TIM[4:1]
● UART
● CAN (register clock, not CAN clock)
After a device reset, all peripheral clocks are enabled. You can disable the clock to any
peripheral by clearing the corresponding PCKEN bit in the Peripheral clock gating register 1
(CLK_PCKENR1) and in the Peripheral clock gating register 2 (CLK_PCKENR2). But you
have to disable properly the peripheral using the appropriate bit, before stopping the
corresponding clock.
To enable a peripheral, you must first enable the corresponding PCKEN bit in the
CLK_PCKENR registers and then set the peripheral enable bit in the peripheral’s control
registers.
The AWU counter is driven by an internal or external clock (LSI or HSE) independent from
f
MASTER
, so that it continues to run even if the register clock to this peripheral is switched off.
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