RM0016 16-bit advanced control timer (TIM1)
Doc ID 14587 Rev 8 205/449
17.7.16 Counter low (TIM1_CNTRL)
Address offset: 0x0F
Reset value: 0x00
17.7.17 Prescaler high (TIM1_PSCRH)
Address offset: 0x10
Reset value: 0x00
17.7.18 Prescaler low (TIM1_PSCRL)
Address offset: 0x11
Reset value: 0x00
76543210
CNT[7:0]
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Bits 7:0 CNT[7:0]: Counter value (LSB).
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PSC[15:8]
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Bits 7:0
PSC[15:8]: Prescaler value (MSB)
The prescaler value divides the CK_PSC clock frequency. The counter clock frequency f
CK_CNT
is
equal to f
CK_PSC
/ (PSCR[15:0]+1). PSCR contain the value which is loaded in the active prescaler
register at each UEV (including when the counter is cleared through the UG bit of the TIM1_EGR
register or through the trigger controller when configured in trigger reset mode). A UEV must be
generated so that a new prescaler value can be taken into account.
76543210
PSC[7:0]
rw rw rw rw rw rw rw rw
Bits 7:0 PSC[7:0]: Prescaler value (LSB)
The prescaler value divides the CK_PSC clock frequency. The counter clock frequency f
CK_CNT
is
equal to f
CK_PSC
/ (PSCR[15:0]+1). PSCR contains the value which is loaded in the active prescaler
register at each UEV (including when the counter is cleared through the UG bit of the TIM1_EGR
register or through the trigger controller when configured in trigger reset mode).
A UEV must be generated so that a new prescaler value can be taken into account.
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