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Universal asynchronous receiver transmitter (UART) RM0016

312/449 Doc ID 14587 Rev 8

Figure 112. UART3 block diagram

WAKE

UNIT

RECEIVER

CONTROL

UART3_SR

TRANSMIT

CONTROL

TXE TC RXNE IDLE

OR/

NF FE

CONTROL

INTERRUPT

UART2_CR1

R8 T8

WAKE

Receive Data Register (RDR)

Receive Shift Register

Read

Transmit Data Register (TDR)

Transmit Shift Register

Write

(DATA REGISTER) UART3_DR

RECEIVER

CLOCK

RECEIVER RATE

TRANSMITTER RATE

MASTER

CONTROL

SBKRWURENTENILIENRIENTCIENTIEN

UART3_CR2

UARTD PCEN PS

PIEN

UART3_CR4

LINEN

UART3_CR3

STOP[1:0]

UARTDIV[11:4]

UARTDIV[15:12]

UARTDIV[3:0]

REN

UART3_BRR2

/UARTDIV

TEN

UART3_TX

UART3_RX

LBDIEN ADD[3:0]LBDL LBDF

LHE

UART3_BRR1

UART3_CR6

LASE

LHIEN

LSFLHDF

LDUM

LSLV

TRANSMITTER

CLOCK

AUTOMATIC RESYNCHRONIZATION

UNIT

Main Page

Default Chapter2
- Table of Contents2
Central Processing Unit (CPU)23
- Introduction23
- CPU Registers23
- Global Configuration Register (CFG_GCR)27
Boot ROM29
Memory and Register Map30
- Memory Layout30
- Register Description Abbreviations33
- Table 4. List of Abbreviations33
Flash Program Memory and Data EEPROM34
- Introduction34
- Glossary34
- Main Flash Memory Features35
- Memory Organization36
- Memory Protection44
- Memory Programming46
- ICP and IAP49
- Table 5. Block Size49
- Table 6. Memory Access Versus Programming Method50
- Flash Registers51
Single Wire Interface Module (SWIM) and Debug Module (DM)57
- Introduction57
- Main Features57
- SWIM Modes57
- Figure 12. SWIM Pin Connection57
Interrupt Controller (ITC)58
- ITC Introduction58
- Interrupt Masking and Processing Flow58
- Interrupts and Low Power Modes62
- Activation Level/Low Power Mode Control62
- Concurrent and Nested Interrupt Management63
- External Interrupts65
- Interrupt Instructions65
- Table 11. Dedicated Interrupt Instruction Set65
- Figure 16. Nested Interrupt Management65
- Interrupt Mapping66
- ITC and EXTI Registers67
Power Supply72
- Figure 17. Power Supply Overview72
Reset (RST)73
- Reset State" and "Under Reset" Definitions73
- Reset Circuit Description73
- Figure 18. Reset Circuit73
- Internal Reset Sources74
- RST Register Description76
  - Reset Status Register (RST_SR)76
- RST Register Map76
- Table 13. RST Register Map76
Clock Control (CLK)77
- Figure 20. Clock Tree78
- Master Clock Sources79
- Master Clock Switching82
- Low Speed Clock Selection85
- CPU Clock Divider85
- Figure 23. Clock Switching Flowchart (Manual Mode Example)85
- Peripheral Clock Gating (PCG)86
- Clock Security System (CSS)87
- Clock-Out Capability (CCO)88
- CLK Interrupts88
- Table 16. CLK Interrupt Requests88
- CLK Register Description89
- CLK Register Map and Reset Values100
- Table 19. CLK Register Map and Reset Values100
Power Management101
- General Considerations101
  - Clock Management for Low Consumption102
- Low Power Modes102
- Additional Analog Power Controls104
  - Fast Flash Wakeup from Halt Mode104
  - Very Low Flash Consumption in Active-Halt Mode104
General Purpose I/O Ports (GPIO)105
- Introduction105
- GPIO Main Features105
- Port Configuration and Usage106
- Reset Configuration108
- Unused I/O Pins108
- Low Power Modes108
- Input Mode Details108
- Output Mode Details109
- GPIO Registers111
Auto-Wakeup (AWU)114
- Introduction114
- LSI Clock Measurement114
- Figure 25. AWU Block Diagram114
- AWU Functional Description115
- AWU Registers118
Beeper (BEEP)120
- Introduction120
- Beeper Functional Description120
- Beeper Registers121
Independent Watchdog (IWDG)122
- Introduction122
- IWDG Functional Description122
- Figure 27. Independent Watchdog (IWDG) Block Diagram122
- Table 28. Watchdog Timeout Period (LSI Clock Frequency = 128 Khz)123
- IWDG Registers124
Window Watchdog (WWDG)126
- Introduction126
- WWDG Main Features126
- WWDG Functional Description126
- Figure 28. Watchdog Block Diagram127
- How to Program the Watchdog Timeout128
- Figure 29. Approximate Timeout Duration128
- WWDG Low Power Modes129
- Table 30. Window Watchdog Timing Example129
- Table 31. Effect of Low Power Modes on WWDG129
- Figure 30. Window Watchdog Timing Diagram129
- Hardware Watchdog Option130
- Using Halt Mode with the WWDG (WWDGHALT Option)130
- WWDG Interrupts130
- WWDG Registers130
  - Control Register (WWDG_CR)130
  - Window Register (WWDG_WR)130
- Window Watchdog Register Map and Reset Values131
- Table 32. WWDG Register Map and Reset Values131
Timer Overview132
- Table 33. Timer Characteristics132
- Timer Feature Comparison133
- Glossary of Timer Signal Names133
- Table 34. Timer Feature Comparison133
- Table 35. Glossary of Internal Timer Signals134
- Figure 44: Control Circuit in Normal Mode, Fck_Psc = Fmaster134
- Table 36. Explanation of Indices'I', 'N', and 'X135
16-Bit Advanced Control Timer (TIM1)136
- Introduction136
- TIM1 Main Features137
- Figure 31. TIM1 General Block Diagram138
- Figure 32. Time Base Unit138
- TIM1 Time Base Unit139
- TIM1 Clock/Trigger Controller149
- TIM1 Capture/Compare Channels163
- TIM1 Interrupts184
- TIM1 Registers185
16-Bit General Purpose Timers (TIM2, TIM3, TIM5)216
- Introduction216
- TIM2/TIM3 Main Features216
- TIM5 Main Features217
- TIM2/TIM3/TIM5 Functional Description217
- TIM2/TIM3/TIM5 Interrupts221
- Figure 87. Output Stage221
- Figure 88. Output Stage of Channel 1221
- TIM2/TIM3/TIM5 Registers223
8-Bit Basic Timer (TIM4, TIM6)243
- Introduction243
- Figure 89. TIM4 Block Diagram243
- Figure 90. TIM6 Block Diagram243
- TIM4 Main Features244
- TIM6 Main Features244
- TIM4/TIM6 Interrupts244
- TIM4/TIM6 Clock Selection244
- TIM4/TIM6 Registers245
Serial Peripheral Interface (SPI)253
- Introduction253
- SPI Main Features253
- SPI Functional Description254
- SPI Registers271
- SPI Register Map and Reset Values277
- Table 47. SPI Register Map and Reset Values277
Inter-Integrated Circuit (I 2 C) Interface278
- Introduction278
- I 2 C Main Features278
- C General Description279
- Figure 100. I 2 C Bus Protocol279
- I 2 C Functional Description281
- I 2 C Low Power Modes291
- Table 48. I 2 C Interface Behavior in Low Power Modes291
- I 2 C Interrupts292
- Table 49. I 2 C Interrupt Requests292
- Figure 109. I2C Interrupt Mapping Diagram292
- I 2 C Registers293
Universal Asynchronous Receiver Transmitter (UART)307
- Introduction307
- Table 52. UART Configurations307
- UART Main Features308
- UART Functional Description309
- LIN Mode Functional Description333
- UART Low Power Modes346
- UART Interrupts346
- Table 59. UART Interface Behavior in Low Power Modes346
- Table 60. UART Interrupt Requests346
- Figure 138. UART Interrupt Mapping Diagram347
- UART Registers348
Controller Area Network (Becan)362
- Introduction362
- Becan Main Features362
- Becan General Description363
- Operating Modes365
- Test Modes367
- Functional Description368
- Interrupts383
- Figure 155. Event Flags and Interrupt Generation383
- Register Access Protection384
- Clock System384
- Becan Low Power Modes384
- Table 67. Becan Behavior in Low Power Modes384
- Becan Registers385
- CAN Register Map407
Analog/Digital Converter (ADC)411
- Introduction411
- ADC Main Features411
- ADC Extended Features411
- Figure 158. ADC1 Block Diagram412
- Figure 159. ADC2 Block Diagram413
- ADC Pins414
- ADC Functional Description414
- ADC Low Power Modes420
- ADC Interrupts420
- Table 72. Low Power Modes420
- Table 73. ADC Interrupts in Single and Non-Buffered Continuous Mode (ADC1 and ADC2)420
- Table 74. ADC Interrupts in Buffered Continuous Mode (ADC1)421
- Table 75. ADC Interrupts in Scan Mode (ADC1)422
- Data Alignment423
- Reading the Conversion Result423
- Figure 163. Right Alignment of Data423
- Figure 164. Left Alignment of Data423
- Schmitt Trigger Disable Registers424
- ADC Registers425

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