16-bit advanced control timer (TIM1) RM0016
166/449 Doc ID 14587 Rev 8
17.5.3 Input capture mode
In input capture mode, the capture/compare registers (TIM1_CCRi) are used to latch the
value of the counter after a transition detected on the corresponding ICi signal. When a
capture occurs, the corresponding CCiIF flag (TIM1_SR1 register) is set.
An interrupt can be sent if it is enabled, by setting the CCiIE bits in the TIM1_IER register. If
a capture occurs while the CCiIF flag is already high, the over-capture flag CCiOF
(TIM1_SR2 register) is set. CCiIF can be cleared by software by writing it to 0 or by reading
the captured data stored in the TIMx_CCRiL registers. CCiOF is cleared by writing it to 0.
Procedure
The following procedure shows how to capture the counter value in TIM1_CCR1, for
example, when TI1 input rises.
1. Select the active input: For example, to link the TIM1_CCR1 register to the TI1 input,
write the CC1S bits to 01 in the TIM1_CCMR1 register. This configures the channel in
input mode and the TIM1_CCR1 register becomes read-only.
2. Program the required input filter duration for the signal to be connected to the timer.
This is done for each TIi input using the ICiF bits in the TIM1_CCMRi registers. For
example, if the input signal is unstable for up to five t
MASTER
cycles when it toggles, the
filter duration must be performed for longer than five clock cycles. The filter bits allow a
duration of eight cycles to be selected by writing them to 0011 in the TIMx_CCMR1
register. With this filter setting, a transition on TI1 is valid only when eight consecutive
samples with the new level have been detected (sampled at f
MASTER
frequency).
3. Select the edge of the active transition on the TI1 channel by writing the CC1P bit to 0
in the TIM1_CCER1 register (rising edge in this case).
4. Program the input prescaler. In this example, the capture needs to be performed at
each valid transition, so the prescaler is disabled (write the IC1PS bits to 00 in the
TIM1_CCMR1 register).
5. Enable capture from the counter into the capture register by setting the CC1E bit in the
TIM1_CCER1 register.
6. If needed, enable the related interrupt request by setting the CC1IE bit in the TIM1_IER
register.
When an input capture occurs:
● The TIM1_CCR1 register gets the value of the counter on the active transition
● The input capture flag (CC1IF) is set. The overcapture flag (CC1OF) is also set if at
least two consecutive captures occur while the flag remains uncleared.
● An interrupt is generated depending on the CC1IE bit
To handle the overcapture event (CC1OF flag), it is recommended to read the data before
the overcapture flag. This avoids missing an overcapture which could occur after reading the
flag and before reading the data.
Note: IC interrupts can be generated by software by setting the corresponding CCiG bits in the
TIM1_EGR register.
To Next Page
Loading...
Need help?
General
