RM0016 16-bit advanced control timer (TIM1)
Doc ID 14587 Rev 8 143/449
17.3.5 Down-counting mode
In down-counting mode, the counter counts from the auto-reload value (content of the
TIM1_ARR register) down to 0. It then restarts from the auto-reload value and generates a
counter underflow and a UEV, if the UDIS bit is 0 in the TIM1_CR1 register.
Figure 37 shows an example of this counting mode.
Figure 37. Counter in down-counting mode
An update event can also be generated by setting the UG bit in the TIM1_EGR register (by
software or by using the clock/trigger mode controller).
The UEV update event can be disabled by software by setting the UDIS bit in TIM1_CR1
register. This is to avoid updating the shadow registers while writing new values in the
preload registers. No update event occurs until the UDIS bit has been written to 0. However,
the counter restarts from the current auto-reload value, whereas the counter of the prescaler
restarts from 0 (without any change to the prescale rate).
In addition, if the URS bit (update request selection) in the TIM1_CR1 register is set, setting
the UG bit generates a UEV without setting the UIF flag (thus no interrupt request is sent).
This avoids generating both update and capture interrupts when clearing the counter on the
capture event.
When an update event occurs, all the registers are updated and the update flag (UIF bit in
TIM1_SR1 register) is set (depending on the URS bit):
● The buffer of the prescaler is reloaded with the preload value (content of the
TIM1_PSCR register),
● The auto-reload shadow register is updated with the preload value (content of the
TIM1_ARR register). Note that the auto-reload is updated before the counter is
reloaded, so that the next period is the expected one.
Figure 38 and Figure 39 show some examples of the counter behavior for different clock
frequencies when TIM1_ARR = 0x36.
In downcounting mode, preload is not normally used. Consequently, the new value is taken
into account in the next period (see Figure 38).
Counter
Time
TIMx_ARR
UnderflowUnderflow Underflow
Underflow
0
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