ST STM8S - ADC Configuration Register 3 (ADC_CR3)

Analog/digital converter (ADC) RM0016
430/449 Doc ID 14587 Rev 8
24.11.6 ADC configuration register 3 (ADC_CR3)
Address offset: 0x23
Reset value: 0x00
Note: This register is not available for ADC2.
76543210
DBUF OVR
Reserved
rw rc_w0
Bit 7 DBUF: Data buffer enable
This bit is set and cleared by software. It is used together with the CONT bit
enable buffered continuous mode (DBUF=1, CONT=1). When DBUF is set,
converted values are stored in the ADC_DBxRH and ADC_DBxRL registers
instead of the ADC_DRH and ADC_DRL registers.
0: Data buffer disabled
1: Data buffer enabled
Bit 6 OVR: Overrun flag
This bit is set by hardware and cleared by software.
0: No overrun
1: An overrun was detected in the data buffer registers.
Refer to Section 24.5.5 on page 416 for more details.
Bits 5:0 Reserved, must be kept cleared.