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Controller area network (beCAN) RM0016

386/449 Doc ID 14587 Rev 8

23.11.2 CAN master status register (CAN_MSR)

Address offset: 0x01

Reset value: 0x002

Bit 1 SLEEP Sleep Mode Request

This bit must be set by software to request the CAN hardware to enter Sleep mode. If the AWUM bit

is not set, the Sleep mode is entered as soon as the current CAN activity (CAN frame transmission

or reception) has completed. If the AWUM bit is set and the CAN bus is active, the CAN does not

enter Sleep mode, the SLEEP bit is not set, and the WKUI bit of the CAN_MSR register is set.

This bit must be cleared by software to exit Sleep mode. It can be cleared by hardware when the

AWUM bit is set and a SOF bit is detected on the CAN Rx signal.

After a reset, the CAN is in Sleep mode and the SLEEP bit is set.

Bit 0 INRQ Initialization Request

The software clears this bit to switch the hardware into normal mode. Once 11 consecutive

recessive bits have been monitored on the Rx signal the CAN hardware is synchronized and ready

for transmission and reception. Hardware signals this event by clearing the INAK bit in the

CAN_MSR register.

Software sets this bit to request the CAN hardware to enter initialization mode. Once software has

set the INRQ bit, the CAN hardware waits until the current CAN activity (transmission or reception) is

completed before entering the initialization mode. Hardware signals this event by setting the INAK

bit in the CAN_MSR register.

76543210

Reserved

RX TX WKUI ERRI SLAK INAK

rrrc_w1rc_w1rr

Bits 7:6 Reserved.

Bit 5 RX Receive

1: The CAN hardware is currently receiver.

Bit 4 TX Transmit

1: The CAN hardware is currently transmitter.

Bit 3 WKUI Wakeup Interrupt

This bit is set by hardware to signal that a SOF bit has been detected while the CAN hardware was

in sleep mode. Setting this bit generates a status change interrupt if the WKUIE bit in the CAN_IER

This bit is cleared by software writing 1.

Bit 2 ERRI Error Interrupt

This bit is set by hardware when a bit of the CAN_ESR has been set on error detection and the

corresponding interrupt in the CAN_EIER is enabled. Setting this bit generates a status change

interrupt if the ERRIE bit in the CAN_EIER register is set.

This bit is cleared by software writing 1.

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