RM0016 Serial peripheral interface (SPI)
Doc ID 14587 Rev 8 253/449
20 Serial peripheral interface (SPI)
20.1 Introduction
The serial peripheral interface (SPI) allows half/ full duplex, synchronous, serial
communication with external devices. The interface can be configured as the master and in
this case it provides the communication clock (SCK) to the external slave device. The
interface is also capable of operating in multi-master configuration.
It may be used for a variety of purposes, including simplex synchronous transfers on 2 lines
with a possible bidirectional data line or reliable communication using CRC checking.
20.2 SPI main features
● Full duplex synchronous transfers (on 3 lines)
● Simplex synchronous transfers on 2 lines with or without a bidirectional data line
● Master or slave operation
● 8 Master mode frequencies (f
MASTER
/2 max.)
● Slave mode frequency (f
MASTER
/2 max.)
● Faster communication - Maximum SPI speed: 10 MHz
● NSS management by hardware or software for both master and slave
● Programmable clock polarity and phase
● Programmable data order with MSB-first or LSB-first shifting
● Dedicated transmission and reception flags with interrupt capability
● SPI bus busy status flag
● Master mode fault and overrun flags with interrupt capability
● Hardware CRC feature for reliable communication:
– CRC value can be transmitted as last byte in Tx mode
– CRC error checking for last received byte
● Wakeup capability:
The MCU wakes up from Low power mode in full or half duplex transmit-only modes
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