RM0016 Universal asynchronous receiver transmitter (UART)
Doc ID 14587 Rev 8 309/449
– Noise error
–Frame error
– Parity error
● 6 interrupt sources with flags
– Transmit data register empty
– Transmission complete
– Receive data register full
– Idle line received
– Overrun error
– Framing error or noise flag
● 2 interrupt vectors
– Transmitter interrupt
– Receiver interrupt when register is full
● Reduced power consumption mode
● Multi-Processor communication - enter into mute mode if address match does not
occur
● Wakeup from mute mode (by idle line detection or address mark detection)
● 2 receiver wakeup modes:
– Address bit (MSB)
– Idle line
22.3 UART functional description
The interface is externally connected to another device by two or three pins (see Figure 110:
UART1 block diagram, Figure 111: UART2 block diagram and Figure 112: UART3 block
diagram). Any UART bidirectional communication requires a minimum of two pins: UART
Receive data input (UART_RX) and UART transmit data output (UART_TX):
UART_RX is the serial data input. Over-sampling techniques are used for data recovery by
discriminating between valid incoming data and noise.
UART_TX is the serial data output. When the transmitter is disabled, the output pin returns
to its I/O port configuration. When the transmitter is enabled and nothing is to be
transmitted, the pin is at high level.
Through these pins, serial data is transmitted and received in normal UART mode as frames
comprising:
● An Idle Line prior to transmission or reception
● A start bit
● A data word (8 or 9 bits) least significant bit first
● 1, 1.5 and 2 Stop bits indicating that the frame is complete
● A status register (UART_SR)
● Data Register (UART_DR)
● 16-bit baud rate prescaler (UART_BRR)
● Guard time Register for use in Smartcard mode
Refer to the register description for the definitions of each bit.
To Next Page
Loading...
Need help?
General
