ST STM8S Reference Manual

Serial peripheral interface (SPI) RM0016
270/449 Doc ID 14587 Rev 8
Overrun condition
An overrun condition occurs, when the master device has sent data bytes and the slave
device has not cleared the RXNE bit resulting from the previous data byte transmitted.
When an overrun condition occurs:
● OVR bit is set and an interrupt is generated if the ERRIE bit is set.
In this case, the receiver buffer contents will not be updated with the newly received data
from the master device. A read to the SPI_DR register returns this byte. All other
subsequently transmitted bytes are lost.
Clearing the OVR bit is done by a read access to the SPI_DR register followed by a read
access to the SPI_SR register.
CRC error
This flag is used to verify the correctness of the value received when the CRCEN bit in the
SPI_CR2 register is set. The CRCERR flag in the SPI_SR register is set if the value
received in the shift register after the SPI_TXCRCR value transmission does not match the
SPI_RXCRCR value. Refer to Chapter 20.3.6: CRC calculation.
20.3.10 SPI low power modes
Using the SPI to wake up the device from Halt mode
When the microcontroller is in Halt mode, the SPI is still capable of responding as a slave
provided the NSS pin is tied low or the SSI bit is reset before entering Halt mode.
When the first sampling edge of data (as defined by the CPHA bit) is detected:
● The WKUP bit is set in the SPI_SR register
● An interrupt is generated if the WKIE bit in the SPI_ICR register is set.
● This interrupt wakes up the device from Halt mode.
● Due to the time needed to restore the system clock, the SPI slave sends or receives a
few data before being able to communicate correctly. It is then mandatory to use the
following protocol:
– A specific value is written into the SPI_DR before entering Halt mode. This value
indicates to the external master that the SPI is in Halt mode
– The external master sends the same byte continuously until it receives from the
SPI slave device a new value other than the unique value indicating the SPI is in
Halt mode. This new value indicates the SPI slave has woken-up and can correctly
communicate.
Table 45. SPI behavior in low power modes
Mode Description
Wait
No effect on SPI.
SPI interrupt events cause the device to exit from Wait mode.
Halt
SPI registers are frozen.
In Halt mode, the SPI is inactive. If the SPI is in master mode, then
communication resumes when the device is woken up by an interrupt with
“wakeup from Halt mode” capability.
If the SPI is in slave mode, then it can wake up the MCU from Halt mode after
detecting the first sampling edge of data.

ST STM8S Specifications

General

Brand	ST
Model	STM8S
Category	Microcontrollers
Language	English